* [PATCH] SWDEV-220585 - Navi12 L1 policy GC regs WAR #1
@ 2020-02-21 20:24 Rohit Khaire
2020-02-25 18:15 ` Deucher, Alexander
0 siblings, 1 reply; 3+ messages in thread
From: Rohit Khaire @ 2020-02-21 20:24 UTC (permalink / raw)
To: amd-gfx; +Cc: Rohit Khaire
This change disables programming of GCVM_L2_CNTL* regs on VF.
Signed-off-by: Rohit Khaire <Rohit.Khaire@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
index b70c7b483c24..e0654a216ab5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
@@ -135,6 +135,10 @@ static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
{
uint32_t tmp;
+ /* These regs are not accessible for VF, PF will program these in SRIOV */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* Setup L2 cache */
tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
@@ -298,9 +302,11 @@ void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev)
ENABLE_ADVANCED_DRIVER_MODEL, 0);
WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
- /* Setup L2 cache */
- WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
- WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);
+ if (!amdgpu_sriov_vf(adev)) {
+ /* Setup L2 cache */
+ WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
+ WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);
+ }
}
/**
--
2.17.1
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^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] SWDEV-220585 - Navi12 L1 policy GC regs WAR #1
2020-02-21 20:24 [PATCH] SWDEV-220585 - Navi12 L1 policy GC regs WAR #1 Rohit Khaire
@ 2020-02-25 18:15 ` Deucher, Alexander
2020-02-25 18:21 ` Khaire, Rohit
0 siblings, 1 reply; 3+ messages in thread
From: Deucher, Alexander @ 2020-02-25 18:15 UTC (permalink / raw)
To: Khaire, Rohit, amd-gfx@lists.freedesktop.org
[-- Attachment #1.1: Type: text/plain, Size: 2473 bytes --]
[AMD Public Use]
Please fix up the patch title. E.g.,
drm/amdgpu: Don't write GCVM_L2_CNTL* regs on navi12 VF
With that fixed, patch is:
Reviewed-by: Alex Deucher@amd.com>
________________________________
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Rohit Khaire <Rohit.Khaire@amd.com>
Sent: Friday, February 21, 2020 3:24 PM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Cc: Khaire, Rohit <Rohit.Khaire@amd.com>
Subject: [PATCH] SWDEV-220585 - Navi12 L1 policy GC regs WAR #1
This change disables programming of GCVM_L2_CNTL* regs on VF.
Signed-off-by: Rohit Khaire <Rohit.Khaire@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
index b70c7b483c24..e0654a216ab5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
@@ -135,6 +135,10 @@ static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
{
uint32_t tmp;
+ /* These regs are not accessible for VF, PF will program these in SRIOV */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* Setup L2 cache */
tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
@@ -298,9 +302,11 @@ void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev)
ENABLE_ADVANCED_DRIVER_MODEL, 0);
WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
- /* Setup L2 cache */
- WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
- WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);
+ if (!amdgpu_sriov_vf(adev)) {
+ /* Setup L2 cache */
+ WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
+ WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);
+ }
}
/**
--
2.17.1
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^ permalink raw reply related [flat|nested] 3+ messages in thread* RE: [PATCH] SWDEV-220585 - Navi12 L1 policy GC regs WAR #1
2020-02-25 18:15 ` Deucher, Alexander
@ 2020-02-25 18:21 ` Khaire, Rohit
0 siblings, 0 replies; 3+ messages in thread
From: Khaire, Rohit @ 2020-02-25 18:21 UTC (permalink / raw)
To: Deucher, Alexander, amd-gfx@lists.freedesktop.org
[-- Attachment #1.1: Type: text/plain, Size: 2993 bytes --]
Thanks Alex!
From: Deucher, Alexander <Alexander.Deucher@amd.com>
Sent: February 25, 2020 1:16 PM
To: Khaire, Rohit <Rohit.Khaire@amd.com>; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] SWDEV-220585 - Navi12 L1 policy GC regs WAR #1
[AMD Public Use]
Please fix up the patch title. E.g.,
drm/amdgpu: Don't write GCVM_L2_CNTL* regs on navi12 VF
With that fixed, patch is:
Reviewed-by: Alex Deucher@amd.com<mailto:Deucher@amd.com>>
________________________________
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org<mailto:amd-gfx-bounces@lists.freedesktop.org>> on behalf of Rohit Khaire <Rohit.Khaire@amd.com<mailto:Rohit.Khaire@amd.com>>
Sent: Friday, February 21, 2020 3:24 PM
To: amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org> <amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>>
Cc: Khaire, Rohit <Rohit.Khaire@amd.com<mailto:Rohit.Khaire@amd.com>>
Subject: [PATCH] SWDEV-220585 - Navi12 L1 policy GC regs WAR #1
This change disables programming of GCVM_L2_CNTL* regs on VF.
Signed-off-by: Rohit Khaire <Rohit.Khaire@amd.com<mailto:Rohit.Khaire@amd.com>>
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
index b70c7b483c24..e0654a216ab5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
@@ -135,6 +135,10 @@ static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
{
uint32_t tmp;
+ /* These regs are not accessible for VF, PF will program these in SRIOV */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* Setup L2 cache */
tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
@@ -298,9 +302,11 @@ void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev)
ENABLE_ADVANCED_DRIVER_MODEL, 0);
WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
- /* Setup L2 cache */
- WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
- WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);
+ if (!amdgpu_sriov_vf(adev)) {
+ /* Setup L2 cache */
+ WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
+ WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);
+ }
}
/**
--
2.17.1
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^ permalink raw reply related [flat|nested] 3+ messages in thread
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2020-02-21 20:24 [PATCH] SWDEV-220585 - Navi12 L1 policy GC regs WAR #1 Rohit Khaire
2020-02-25 18:15 ` Deucher, Alexander
2020-02-25 18:21 ` Khaire, Rohit
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