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From: Matthias Kaehlcke <mka@chromium.org>
To: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
	devicetree@vger.kernel.org, seanpaul@chromium.org,
	abhinavk@codeaurora.org, hoegsberg@google.com,
	dri-devel@lists.freedesktop.org
Subject: Re: [DPU PATCH v3 4/5] drm/msm/dp: add support for DP PLL driver
Date: Thu, 27 Feb 2020 15:41:34 -0800	[thread overview]
Message-ID: <20200227234134.GL24720@google.com> (raw)
In-Reply-To: <0101016ec6de9b5b-cd61a0a2-9ae4-4ca1-a3a4-0ad2e8783e20-000000@us-west-2.amazonses.com>

On Mon, Dec 02, 2019 at 01:48:27PM +0000, Chandan Uddaraju wrote:
> Add the needed DP PLL specific files to support
> display port interface on msm targets.
> 
> The DP driver calls the DP PLL driver registration.
> The DP driver sets the link and pixel clock sources.
> 
> Changes in v2:
> -- Update copyright markings on all relevant files.
> -- Use DRM_DEBUG_DP for debug msgs.
> 
> Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
> ---
> diff --git a/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c b/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c
> new file mode 100644
> index 0000000..6ef2492
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c
>
> ...
>
> +static u8 dp_mux_get_parent_10nm(struct clk_hw *hw)
> +{
> +	u32 auxclk_div = 0;
> +	struct dp_pll_10nm_pclksel *pclksel = to_pll_10nm_pclksel(hw);
> +	struct dp_pll_10nm *dp_res = pclksel->pll;
> +	u8 val = 0;
> +
> +	DRM_ERROR("clk_hw->init->name = %s\n", hw->init->name);

drive-by comment: DRM_ERROR doesn't seem the right level, DRM_DEBUG_DP
would probably be more adequate.

Also I found this line triggers a NULL pointer dereference on a SC7180
system, where clk_hw->init is NULL.

WARNING: multiple messages have this Message-ID (diff)
From: Matthias Kaehlcke <mka@chromium.org>
To: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	abhinavk@codeaurora.org, seanpaul@chromium.org,
	dri-devel@lists.freedesktop.org, hoegsberg@google.com,
	freedreno@lists.freedesktop.org
Subject: Re: [DPU PATCH v3 4/5] drm/msm/dp: add support for DP PLL driver
Date: Thu, 27 Feb 2020 15:41:34 -0800	[thread overview]
Message-ID: <20200227234134.GL24720@google.com> (raw)
In-Reply-To: <0101016ec6de9b5b-cd61a0a2-9ae4-4ca1-a3a4-0ad2e8783e20-000000@us-west-2.amazonses.com>

On Mon, Dec 02, 2019 at 01:48:27PM +0000, Chandan Uddaraju wrote:
> Add the needed DP PLL specific files to support
> display port interface on msm targets.
> 
> The DP driver calls the DP PLL driver registration.
> The DP driver sets the link and pixel clock sources.
> 
> Changes in v2:
> -- Update copyright markings on all relevant files.
> -- Use DRM_DEBUG_DP for debug msgs.
> 
> Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
> ---
> diff --git a/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c b/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c
> new file mode 100644
> index 0000000..6ef2492
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c
>
> ...
>
> +static u8 dp_mux_get_parent_10nm(struct clk_hw *hw)
> +{
> +	u32 auxclk_div = 0;
> +	struct dp_pll_10nm_pclksel *pclksel = to_pll_10nm_pclksel(hw);
> +	struct dp_pll_10nm *dp_res = pclksel->pll;
> +	u8 val = 0;
> +
> +	DRM_ERROR("clk_hw->init->name = %s\n", hw->init->name);

drive-by comment: DRM_ERROR doesn't seem the right level, DRM_DEBUG_DP
would probably be more adequate.

Also I found this line triggers a NULL pointer dereference on a SC7180
system, where clk_hw->init is NULL.
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  reply	other threads:[~2020-02-27 23:41 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <1575294437-6129-1-git-send-email-chandanu@codeaurora.org>
2019-12-02 13:47 ` [DPU PATCH v3 2/5] drm: add constant N value in helper file Chandan Uddaraju
2019-12-02 13:47 ` Chandan Uddaraju
2019-12-02 14:13   ` Jani Nikula
2019-12-02 14:13     ` Jani Nikula
2019-12-02 14:13     ` Jani Nikula
2019-12-02 13:47 ` [DPU PATCH v3 1/5] dt-bindings: msm/dp: add bindings of DP/DP-PLL driver for Snapdragon 845 Chandan Uddaraju
2019-12-13 22:58   ` Rob Herring
2019-12-13 22:58     ` Rob Herring
2019-12-13 23:04   ` Jeffrey Hugo
2019-12-13 23:04     ` Jeffrey Hugo
2019-12-02 13:48 ` [DPU PATCH v3 3/5] drm/msm/dp: add displayPort driver support Chandan Uddaraju
2019-12-02 13:48 ` [DPU PATCH v3 5/5] drm/msm/dpu: add display port support in DPU Chandan Uddaraju
     [not found] ` <1575294437-6129-1-git-send-email-chandanu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2019-12-02 13:47   ` [DPU PATCH v3 1/5] dt-bindings: msm/dp: add bindings of DP/DP-PLL driver for Snapdragon 845 Chandan Uddaraju
2019-12-02 13:47     ` Chandan Uddaraju
2019-12-02 13:48   ` [DPU PATCH v3 5/5] drm/msm/dpu: add display port support in DPU Chandan Uddaraju
2019-12-02 13:48     ` Chandan Uddaraju
2019-12-02 13:48   ` [DPU PATCH v3 3/5] drm/msm/dp: add displayPort driver support Chandan Uddaraju
2019-12-02 13:48     ` Chandan Uddaraju
2020-02-27 21:54     ` Matthias Kaehlcke
2020-02-27 21:54       ` Matthias Kaehlcke
2020-02-28  0:43       ` Matthias Kaehlcke
2020-02-28  0:43         ` Matthias Kaehlcke
2020-02-28 21:49     ` Matthias Kaehlcke
2020-02-28 21:49       ` Matthias Kaehlcke
     [not found]       ` <fe3f72c14d570d805996a889944fae35@codeaurora.org>
     [not found]         ` <BYAPR02MB5288D92EF7422BF5C86FC45BA9E70@BYAPR02MB5288.namprd02.prod.outlook.com>
2020-03-02 23:47           ` FW: " varar
2020-03-02 23:47             ` varar
2020-03-03 20:24             ` Matthias Kaehlcke
2019-12-02 13:48 ` [DPU PATCH v3 4/5] drm/msm/dp: add support for DP PLL driver Chandan Uddaraju
2020-02-27 23:41   ` Matthias Kaehlcke [this message]
2020-02-27 23:41     ` Matthias Kaehlcke
2019-12-02 13:48 ` Chandan Uddaraju
     [not found] ` <0101016ec6df0d33-edb8acfc-a6f1-486e-a8db-38ec498951ed-000000@us-west-2.amazonses.com>
2019-12-02 16:48   ` [DPU PATCH v3 3/5] drm/msm/dp: add displayPort driver support Rob Clark
2019-12-02 16:48     ` Rob Clark
     [not found]     ` <3130b7844837a8caaa10f9f4f5633eab@codeaurora.org>
2020-02-14  0:37       ` chandanu
2020-02-14  0:37         ` chandanu
2019-12-02 18:59   ` Rob Clark
2019-12-02 18:59     ` Rob Clark

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