* [PATCH v5 1/4] PCI: Add 32 GT/s decoding in some macros
2020-02-29 3:07 [PATCH v5 0/4] Improve link speed presentation process Bjorn Helgaas
@ 2020-02-29 3:07 ` Bjorn Helgaas
2020-02-29 3:07 ` [PATCH v5 2/4] PCI: Add pci_speed_string() Bjorn Helgaas
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Bjorn Helgaas @ 2020-02-29 3:07 UTC (permalink / raw)
To: Yicong Yang; +Cc: Jay Fang, huangdaode, linux-pci, Bjorn Helgaas
From: Yicong Yang <yangyicong@hisilicon.com>
Link speed 32.0 GT/s is supported in PCIe r5.0. Add this speed to
PCIE_SPEED2STR() and PCIE_SPEED2MBS_ENC() to correctly decode it.
This is complementary to de76cda215d5 ("PCI: Decode PCIe 32 GT/s link
speed").
Link: https://lore.kernel.org/r/1581937984-40353-2-git-send-email-yangyicong@hisilicon.com
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/pci.h | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 6394e7746fb5..f65912e0f30d 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -294,7 +294,8 @@ void pci_bus_put(struct pci_bus *bus);
/* PCIe link information */
#define PCIE_SPEED2STR(speed) \
- ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \
+ ((speed) == PCIE_SPEED_32_0GT ? "32 GT/s" : \
+ (speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \
(speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \
(speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \
(speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \
@@ -302,7 +303,8 @@ void pci_bus_put(struct pci_bus *bus);
/* PCIe speed to Mb/s reduced by encoding overhead */
#define PCIE_SPEED2MBS_ENC(speed) \
- ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
+ ((speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
+ (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
(speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
(speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
(speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
--
2.25.0.265.gbab2e86ba0-goog
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v5 2/4] PCI: Add pci_speed_string()
2020-02-29 3:07 [PATCH v5 0/4] Improve link speed presentation process Bjorn Helgaas
2020-02-29 3:07 ` [PATCH v5 1/4] PCI: Add 32 GT/s decoding in some macros Bjorn Helgaas
@ 2020-02-29 3:07 ` Bjorn Helgaas
2020-02-29 3:07 ` [PATCH v5 3/4] PCI: Use pci_speed_string() for all PCI/PCI-X/PCIe strings Bjorn Helgaas
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Bjorn Helgaas @ 2020-02-29 3:07 UTC (permalink / raw)
To: Yicong Yang; +Cc: Jay Fang, huangdaode, linux-pci, Bjorn Helgaas
From: Bjorn Helgaas <bhelgaas@google.com>
Add pci_speed_string() to return a text description of the supplied bus or
link speed. The slot code previously used the private
pci_bus_speed_strings[] array for this purpose, but adding this interface
will enable us to consolidate similar code elsewhere.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/pci.h | 1 +
drivers/pci/probe.c | 38 ++++++++++++++++++++++++++++++++++++++
drivers/pci/slot.c | 38 +-------------------------------------
include/linux/pci.h | 2 +-
4 files changed, 41 insertions(+), 38 deletions(-)
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index f65912e0f30d..809753b10fad 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -310,6 +310,7 @@ void pci_bus_put(struct pci_bus *bus);
(speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
0)
+const char *pci_speed_string(enum pci_bus_speed speed);
enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 512cb4312ddd..3a1aba39ad67 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -640,6 +640,7 @@ void pci_free_host_bridge(struct pci_host_bridge *bridge)
}
EXPORT_SYMBOL(pci_free_host_bridge);
+/* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */
static const unsigned char pcix_bus_speed[] = {
PCI_SPEED_UNKNOWN, /* 0 */
PCI_SPEED_66MHz_PCIX, /* 1 */
@@ -659,6 +660,7 @@ static const unsigned char pcix_bus_speed[] = {
PCI_SPEED_133MHz_PCIX_533 /* F */
};
+/* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */
const unsigned char pcie_link_speed[] = {
PCI_SPEED_UNKNOWN, /* 0 */
PCIE_SPEED_2_5GT, /* 1 */
@@ -678,6 +680,42 @@ const unsigned char pcie_link_speed[] = {
PCI_SPEED_UNKNOWN /* F */
};
+const char *pci_speed_string(enum pci_bus_speed speed)
+{
+ /* Indexed by the pci_bus_speed enum */
+ static const char *speed_strings[] = {
+ "33 MHz PCI", /* 0x00 */
+ "66 MHz PCI", /* 0x01 */
+ "66 MHz PCI-X", /* 0x02 */
+ "100 MHz PCI-X", /* 0x03 */
+ "133 MHz PCI-X", /* 0x04 */
+ NULL, /* 0x05 */
+ NULL, /* 0x06 */
+ NULL, /* 0x07 */
+ NULL, /* 0x08 */
+ "66 MHz PCI-X 266", /* 0x09 */
+ "100 MHz PCI-X 266", /* 0x0a */
+ "133 MHz PCI-X 266", /* 0x0b */
+ "Unknown AGP", /* 0x0c */
+ "1x AGP", /* 0x0d */
+ "2x AGP", /* 0x0e */
+ "4x AGP", /* 0x0f */
+ "8x AGP", /* 0x10 */
+ "66 MHz PCI-X 533", /* 0x11 */
+ "100 MHz PCI-X 533", /* 0x12 */
+ "133 MHz PCI-X 533", /* 0x13 */
+ "2.5 GT/s PCIe", /* 0x14 */
+ "5.0 GT/s PCIe", /* 0x15 */
+ "8.0 GT/s PCIe", /* 0x16 */
+ "16.0 GT/s PCIe", /* 0x17 */
+ "32.0 GT/s PCIe", /* 0x18 */
+ };
+
+ if (speed < ARRAY_SIZE(speed_strings))
+ return speed_strings[speed];
+ return "Unknown";
+}
+
void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
{
bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
diff --git a/drivers/pci/slot.c b/drivers/pci/slot.c
index ae4aa0e1f2f4..cc386ef2fa12 100644
--- a/drivers/pci/slot.c
+++ b/drivers/pci/slot.c
@@ -49,45 +49,9 @@ static ssize_t address_read_file(struct pci_slot *slot, char *buf)
slot->number);
}
-/* these strings match up with the values in pci_bus_speed */
-static const char *pci_bus_speed_strings[] = {
- "33 MHz PCI", /* 0x00 */
- "66 MHz PCI", /* 0x01 */
- "66 MHz PCI-X", /* 0x02 */
- "100 MHz PCI-X", /* 0x03 */
- "133 MHz PCI-X", /* 0x04 */
- NULL, /* 0x05 */
- NULL, /* 0x06 */
- NULL, /* 0x07 */
- NULL, /* 0x08 */
- "66 MHz PCI-X 266", /* 0x09 */
- "100 MHz PCI-X 266", /* 0x0a */
- "133 MHz PCI-X 266", /* 0x0b */
- "Unknown AGP", /* 0x0c */
- "1x AGP", /* 0x0d */
- "2x AGP", /* 0x0e */
- "4x AGP", /* 0x0f */
- "8x AGP", /* 0x10 */
- "66 MHz PCI-X 533", /* 0x11 */
- "100 MHz PCI-X 533", /* 0x12 */
- "133 MHz PCI-X 533", /* 0x13 */
- "2.5 GT/s PCIe", /* 0x14 */
- "5.0 GT/s PCIe", /* 0x15 */
- "8.0 GT/s PCIe", /* 0x16 */
- "16.0 GT/s PCIe", /* 0x17 */
- "32.0 GT/s PCIe", /* 0x18 */
-};
-
static ssize_t bus_speed_read(enum pci_bus_speed speed, char *buf)
{
- const char *speed_string;
-
- if (speed < ARRAY_SIZE(pci_bus_speed_strings))
- speed_string = pci_bus_speed_strings[speed];
- else
- speed_string = "Unknown";
-
- return sprintf(buf, "%s\n", speed_string);
+ return sprintf(buf, "%s\n", pci_speed_string(speed));
}
static ssize_t max_speed_read_file(struct pci_slot *slot, char *buf)
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 3840a541a9de..76f4806a154c 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -236,7 +236,7 @@ enum pcie_link_width {
PCIE_LNK_WIDTH_UNKNOWN = 0xff,
};
-/* Based on the PCI Hotplug Spec, but some values are made up by us */
+/* See matching string table in pci_speed_string() */
enum pci_bus_speed {
PCI_SPEED_33MHz = 0x00,
PCI_SPEED_66MHz = 0x01,
--
2.25.0.265.gbab2e86ba0-goog
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v5 3/4] PCI: Use pci_speed_string() for all PCI/PCI-X/PCIe strings
2020-02-29 3:07 [PATCH v5 0/4] Improve link speed presentation process Bjorn Helgaas
2020-02-29 3:07 ` [PATCH v5 1/4] PCI: Add 32 GT/s decoding in some macros Bjorn Helgaas
2020-02-29 3:07 ` [PATCH v5 2/4] PCI: Add pci_speed_string() Bjorn Helgaas
@ 2020-02-29 3:07 ` Bjorn Helgaas
2020-02-29 9:10 ` Yicong Yang
2020-02-29 3:07 ` [PATCH v5 4/4] PCI: Add PCIE_LNKCAP2_SLS2SPEED() macro Bjorn Helgaas
2020-03-02 23:46 ` [PATCH v5 0/4] Improve link speed presentation process Bjorn Helgaas
4 siblings, 1 reply; 8+ messages in thread
From: Bjorn Helgaas @ 2020-02-29 3:07 UTC (permalink / raw)
To: Yicong Yang; +Cc: Jay Fang, huangdaode, linux-pci, Bjorn Helgaas
From: Bjorn Helgaas <bhelgaas@google.com>
Previously some PCI speed strings came from pci_speed_string(), some came
from the PCIe-specific PCIE_SPEED2STR(), and some came from a PCIe-specific
switch statement. These methods were inconsistent:
pci_speed_string() PCIE_SPEED2STR() switch
------------------ ---------------- ------
33 MHz PCI
...
2.5 GT/s PCIe 2.5 GT/s 2.5 GT/s
5.0 GT/s PCIe 5 GT/s 5 GT/s
8.0 GT/s PCIe 8 GT/s 8 GT/s
16.0 GT/s PCIe 16 GT/s 16 GT/s
32.0 GT/s PCIe 32 GT/s 32 GT/s
Standardize on pci_speed_string() as the single source of these strings.
Note that this adds ".0" and "PCIe" to some messages, including sysfs
"max_link_speed" files, a brcmstb "link up" message, and the link status
dmesg logging, e.g.,
nvme 0000:01:00.0: 16.000 Gb/s available PCIe bandwidth, limited by 5.0 GT/s PCIe x4 link at 0000:00:01.1 (capable of 31.504 Gb/s with 8.0 GT/s PCIe x4 link)
I think it's better to standardize on a single version of the speed text.
Previously we had strings like this:
/sys/bus/pci/slots/0/cur_bus_speed: 8.0 GT/s PCIe
/sys/bus/pci/slots/0/max_bus_speed: 8.0 GT/s PCIe
/sys/devices/pci0000:00/0000:00:1c.0/current_link_speed: 8 GT/s
/sys/devices/pci0000:00/0000:00:1c.0/max_link_speed: 8 GT/s
This changes the latter two to match the slots files:
/sys/devices/pci0000:00/0000:00:1c.0/current_link_speed: 8.0 GT/s PCIe
/sys/devices/pci0000:00/0000:00:1c.0/max_link_speed: 8.0 GT/s PCIe
Based-on-patch by: Yicong Yang <yangyicong@hisilicon.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/controller/pcie-brcmstb.c | 3 +--
drivers/pci/pci-sysfs.c | 27 +++++----------------------
drivers/pci/pci.c | 6 +++---
drivers/pci/pci.h | 9 ---------
4 files changed, 9 insertions(+), 36 deletions(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index d20aabc26273..41e88f1667bf 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -823,8 +823,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
cls = FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta);
nlw = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);
- dev_info(dev, "link up, %s x%u %s\n",
- PCIE_SPEED2STR(cls + PCI_SPEED_133MHz_PCIX_533),
+ dev_info(dev, "link up, %s x%u %s\n", pci_speed_string(cls),
nlw, ssc_good ? "(SSC)" : "(!SSC)");
/* PCIe->SCB endian mode for BAR */
diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
index 13f766db0684..d123d1087061 100644
--- a/drivers/pci/pci-sysfs.c
+++ b/drivers/pci/pci-sysfs.c
@@ -156,7 +156,8 @@ static ssize_t max_link_speed_show(struct device *dev,
{
struct pci_dev *pdev = to_pci_dev(dev);
- return sprintf(buf, "%s\n", PCIE_SPEED2STR(pcie_get_speed_cap(pdev)));
+ return sprintf(buf, "%s\n",
+ pci_speed_string(pcie_get_speed_cap(pdev)));
}
static DEVICE_ATTR_RO(max_link_speed);
@@ -175,33 +176,15 @@ static ssize_t current_link_speed_show(struct device *dev,
struct pci_dev *pci_dev = to_pci_dev(dev);
u16 linkstat;
int err;
- const char *speed;
+ enum pci_bus_speed speed;
err = pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &linkstat);
if (err)
return -EINVAL;
- switch (linkstat & PCI_EXP_LNKSTA_CLS) {
- case PCI_EXP_LNKSTA_CLS_32_0GB:
- speed = "32 GT/s";
- break;
- case PCI_EXP_LNKSTA_CLS_16_0GB:
- speed = "16 GT/s";
- break;
- case PCI_EXP_LNKSTA_CLS_8_0GB:
- speed = "8 GT/s";
- break;
- case PCI_EXP_LNKSTA_CLS_5_0GB:
- speed = "5 GT/s";
- break;
- case PCI_EXP_LNKSTA_CLS_2_5GB:
- speed = "2.5 GT/s";
- break;
- default:
- speed = "Unknown speed";
- }
+ speed = pcie_link_speed[linkstat & PCI_EXP_LNKSTA_CLS];
- return sprintf(buf, "%s\n", speed);
+ return sprintf(buf, "%s\n", pci_speed_string(speed));
}
static DEVICE_ATTR_RO(current_link_speed);
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index d828ca835a98..421587badecf 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -5872,14 +5872,14 @@ void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
if (bw_avail >= bw_cap && verbose)
pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
bw_cap / 1000, bw_cap % 1000,
- PCIE_SPEED2STR(speed_cap), width_cap);
+ pci_speed_string(speed_cap), width_cap);
else if (bw_avail < bw_cap)
pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
bw_avail / 1000, bw_avail % 1000,
- PCIE_SPEED2STR(speed), width,
+ pci_speed_string(speed), width,
limiting_dev ? pci_name(limiting_dev) : "<unknown>",
bw_cap / 1000, bw_cap % 1000,
- PCIE_SPEED2STR(speed_cap), width_cap);
+ pci_speed_string(speed_cap), width_cap);
}
/**
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 809753b10fad..01f5d7f449a5 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -292,15 +292,6 @@ void pci_disable_bridge_window(struct pci_dev *dev);
struct pci_bus *pci_bus_get(struct pci_bus *bus);
void pci_bus_put(struct pci_bus *bus);
-/* PCIe link information */
-#define PCIE_SPEED2STR(speed) \
- ((speed) == PCIE_SPEED_32_0GT ? "32 GT/s" : \
- (speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \
- (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \
- (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \
- (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \
- "Unknown speed")
-
/* PCIe speed to Mb/s reduced by encoding overhead */
#define PCIE_SPEED2MBS_ENC(speed) \
((speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
--
2.25.0.265.gbab2e86ba0-goog
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v5 3/4] PCI: Use pci_speed_string() for all PCI/PCI-X/PCIe strings
2020-02-29 3:07 ` [PATCH v5 3/4] PCI: Use pci_speed_string() for all PCI/PCI-X/PCIe strings Bjorn Helgaas
@ 2020-02-29 9:10 ` Yicong Yang
2020-03-02 23:45 ` Bjorn Helgaas
0 siblings, 1 reply; 8+ messages in thread
From: Yicong Yang @ 2020-02-29 9:10 UTC (permalink / raw)
To: Bjorn Helgaas; +Cc: Jay Fang, huangdaode, linux-pci, Bjorn Helgaas
Hi Bjorn,
On 2020/2/29 11:07, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <bhelgaas@google.com>
>
> Previously some PCI speed strings came from pci_speed_string(), some came
> from the PCIe-specific PCIE_SPEED2STR(), and some came from a PCIe-specific
> switch statement. These methods were inconsistent:
>
> pci_speed_string() PCIE_SPEED2STR() switch
> ------------------ ---------------- ------
> 33 MHz PCI
> ...
> 2.5 GT/s PCIe 2.5 GT/s 2.5 GT/s
> 5.0 GT/s PCIe 5 GT/s 5 GT/s
> 8.0 GT/s PCIe 8 GT/s 8 GT/s
> 16.0 GT/s PCIe 16 GT/s 16 GT/s
> 32.0 GT/s PCIe 32 GT/s 32 GT/s
>
> Standardize on pci_speed_string() as the single source of these strings.
>
> Note that this adds ".0" and "PCIe" to some messages, including sysfs
> "max_link_speed" files, a brcmstb "link up" message, and the link status
> dmesg logging, e.g.,
>
> nvme 0000:01:00.0: 16.000 Gb/s available PCIe bandwidth, limited by 5.0 GT/s PCIe x4 link at 0000:00:01.1 (capable of 31.504 Gb/s with 8.0 GT/s PCIe x4 link)
>
> I think it's better to standardize on a single version of the speed text.
> Previously we had strings like this:
>
> /sys/bus/pci/slots/0/cur_bus_speed: 8.0 GT/s PCIe
> /sys/bus/pci/slots/0/max_bus_speed: 8.0 GT/s PCIe
> /sys/devices/pci0000:00/0000:00:1c.0/current_link_speed: 8 GT/s
> /sys/devices/pci0000:00/0000:00:1c.0/max_link_speed: 8 GT/s
>
> This changes the latter two to match the slots files:
>
> /sys/devices/pci0000:00/0000:00:1c.0/current_link_speed: 8.0 GT/s PCIe
> /sys/devices/pci0000:00/0000:00:1c.0/max_link_speed: 8.0 GT/s PCIe
>
> Based-on-patch by: Yicong Yang <yangyicong@hisilicon.com>
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> ---
> drivers/pci/controller/pcie-brcmstb.c | 3 +--
> drivers/pci/pci-sysfs.c | 27 +++++----------------------
> drivers/pci/pci.c | 6 +++---
> drivers/pci/pci.h | 9 ---------
> 4 files changed, 9 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> index d20aabc26273..41e88f1667bf 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -823,8 +823,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
> cls = FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta);
> nlw = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);
> - dev_info(dev, "link up, %s x%u %s\n",
> - PCIE_SPEED2STR(cls + PCI_SPEED_133MHz_PCIX_533),
> + dev_info(dev, "link up, %s x%u %s\n", pci_speed_string(cls),
> nlw, ssc_good ? "(SSC)" : "(!SSC)");
Here comes the problem. cls is not a pci_bus_speed enumerate. The PCIe link speed decodes
from PCI_EXP_LNKSTA is from 0x000, we'll get the *wrong* string if passing cls directly to
pci_speed_string(). pcie_link_speed[](drivers/pci/probe.c, line 662) array should be used
here to do the conversion.
+ dev_info(dev, "link up, %s x%u %s\n", pci_speed_string(pcie_link_speed[cls]),
nlw, ssc_good ? "(SSC)" : "(!SSC)";
The other parts of the series are fine with me.
Regards,
Yicong Yang
>
> /* PCIe->SCB endian mode for BAR */
> diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
> index 13f766db0684..d123d1087061 100644
> --- a/drivers/pci/pci-sysfs.c
> +++ b/drivers/pci/pci-sysfs.c
> @@ -156,7 +156,8 @@ static ssize_t max_link_speed_show(struct device *dev,
> {
> struct pci_dev *pdev = to_pci_dev(dev);
>
> - return sprintf(buf, "%s\n", PCIE_SPEED2STR(pcie_get_speed_cap(pdev)));
> + return sprintf(buf, "%s\n",
> + pci_speed_string(pcie_get_speed_cap(pdev)));
> }
> static DEVICE_ATTR_RO(max_link_speed);
>
> @@ -175,33 +176,15 @@ static ssize_t current_link_speed_show(struct device *dev,
> struct pci_dev *pci_dev = to_pci_dev(dev);
> u16 linkstat;
> int err;
> - const char *speed;
> + enum pci_bus_speed speed;
>
> err = pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &linkstat);
> if (err)
> return -EINVAL;
>
> - switch (linkstat & PCI_EXP_LNKSTA_CLS) {
> - case PCI_EXP_LNKSTA_CLS_32_0GB:
> - speed = "32 GT/s";
> - break;
> - case PCI_EXP_LNKSTA_CLS_16_0GB:
> - speed = "16 GT/s";
> - break;
> - case PCI_EXP_LNKSTA_CLS_8_0GB:
> - speed = "8 GT/s";
> - break;
> - case PCI_EXP_LNKSTA_CLS_5_0GB:
> - speed = "5 GT/s";
> - break;
> - case PCI_EXP_LNKSTA_CLS_2_5GB:
> - speed = "2.5 GT/s";
> - break;
> - default:
> - speed = "Unknown speed";
> - }
> + speed = pcie_link_speed[linkstat & PCI_EXP_LNKSTA_CLS];
>
> - return sprintf(buf, "%s\n", speed);
> + return sprintf(buf, "%s\n", pci_speed_string(speed));
> }
> static DEVICE_ATTR_RO(current_link_speed);
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index d828ca835a98..421587badecf 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -5872,14 +5872,14 @@ void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
> if (bw_avail >= bw_cap && verbose)
> pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
> bw_cap / 1000, bw_cap % 1000,
> - PCIE_SPEED2STR(speed_cap), width_cap);
> + pci_speed_string(speed_cap), width_cap);
> else if (bw_avail < bw_cap)
> pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
> bw_avail / 1000, bw_avail % 1000,
> - PCIE_SPEED2STR(speed), width,
> + pci_speed_string(speed), width,
> limiting_dev ? pci_name(limiting_dev) : "<unknown>",
> bw_cap / 1000, bw_cap % 1000,
> - PCIE_SPEED2STR(speed_cap), width_cap);
> + pci_speed_string(speed_cap), width_cap);
> }
>
> /**
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> index 809753b10fad..01f5d7f449a5 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -292,15 +292,6 @@ void pci_disable_bridge_window(struct pci_dev *dev);
> struct pci_bus *pci_bus_get(struct pci_bus *bus);
> void pci_bus_put(struct pci_bus *bus);
>
> -/* PCIe link information */
> -#define PCIE_SPEED2STR(speed) \
> - ((speed) == PCIE_SPEED_32_0GT ? "32 GT/s" : \
> - (speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \
> - (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \
> - (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \
> - (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \
> - "Unknown speed")
> -
> /* PCIe speed to Mb/s reduced by encoding overhead */
> #define PCIE_SPEED2MBS_ENC(speed) \
> ((speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v5 3/4] PCI: Use pci_speed_string() for all PCI/PCI-X/PCIe strings
2020-02-29 9:10 ` Yicong Yang
@ 2020-03-02 23:45 ` Bjorn Helgaas
0 siblings, 0 replies; 8+ messages in thread
From: Bjorn Helgaas @ 2020-03-02 23:45 UTC (permalink / raw)
To: Yicong Yang; +Cc: Jay Fang, huangdaode, linux-pci
On Sat, Feb 29, 2020 at 05:10:38PM +0800, Yicong Yang wrote:
> On 2020/2/29 11:07, Bjorn Helgaas wrote:
> > From: Bjorn Helgaas <bhelgaas@google.com>
> >
> > Previously some PCI speed strings came from pci_speed_string(), some came
> > from the PCIe-specific PCIE_SPEED2STR(), and some came from a PCIe-specific
> > switch statement. These methods were inconsistent:
> >
> > pci_speed_string() PCIE_SPEED2STR() switch
> > ------------------ ---------------- ------
> > 33 MHz PCI
> > ...
> > 2.5 GT/s PCIe 2.5 GT/s 2.5 GT/s
> > 5.0 GT/s PCIe 5 GT/s 5 GT/s
> > 8.0 GT/s PCIe 8 GT/s 8 GT/s
> > 16.0 GT/s PCIe 16 GT/s 16 GT/s
> > 32.0 GT/s PCIe 32 GT/s 32 GT/s
> >
> > Standardize on pci_speed_string() as the single source of these strings.
> >
> > Note that this adds ".0" and "PCIe" to some messages, including sysfs
> > "max_link_speed" files, a brcmstb "link up" message, and the link status
> > dmesg logging, e.g.,
> >
> > nvme 0000:01:00.0: 16.000 Gb/s available PCIe bandwidth, limited by 5.0 GT/s PCIe x4 link at 0000:00:01.1 (capable of 31.504 Gb/s with 8.0 GT/s PCIe x4 link)
> >
> > I think it's better to standardize on a single version of the speed text.
> > Previously we had strings like this:
> >
> > /sys/bus/pci/slots/0/cur_bus_speed: 8.0 GT/s PCIe
> > /sys/bus/pci/slots/0/max_bus_speed: 8.0 GT/s PCIe
> > /sys/devices/pci0000:00/0000:00:1c.0/current_link_speed: 8 GT/s
> > /sys/devices/pci0000:00/0000:00:1c.0/max_link_speed: 8 GT/s
> >
> > This changes the latter two to match the slots files:
> >
> > /sys/devices/pci0000:00/0000:00:1c.0/current_link_speed: 8.0 GT/s PCIe
> > /sys/devices/pci0000:00/0000:00:1c.0/max_link_speed: 8.0 GT/s PCIe
> >
> > Based-on-patch by: Yicong Yang <yangyicong@hisilicon.com>
> > Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> > ---
> > drivers/pci/controller/pcie-brcmstb.c | 3 +--
> > drivers/pci/pci-sysfs.c | 27 +++++----------------------
> > drivers/pci/pci.c | 6 +++---
> > drivers/pci/pci.h | 9 ---------
> > 4 files changed, 9 insertions(+), 36 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> > index d20aabc26273..41e88f1667bf 100644
> > --- a/drivers/pci/controller/pcie-brcmstb.c
> > +++ b/drivers/pci/controller/pcie-brcmstb.c
> > @@ -823,8 +823,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> > lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
> > cls = FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta);
> > nlw = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);
> > - dev_info(dev, "link up, %s x%u %s\n",
> > - PCIE_SPEED2STR(cls + PCI_SPEED_133MHz_PCIX_533),
> > + dev_info(dev, "link up, %s x%u %s\n", pci_speed_string(cls),
> > nlw, ssc_good ? "(SSC)" : "(!SSC)");
>
> Here comes the problem. cls is not a pci_bus_speed enumerate. The
> PCIe link speed decodes from PCI_EXP_LNKSTA is from 0x000, we'll get
> the *wrong* string if passing cls directly to pci_speed_string().
> pcie_link_speed[](drivers/pci/probe.c, line 662) array should be
> used here to do the conversion.
>
> + dev_info(dev, "link up, %s x%u %s\n", pci_speed_string(pcie_link_speed[cls]),
> nlw, ssc_good ? "(SSC)" : "(!SSC)";
Oh, right, thanks!
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v5 4/4] PCI: Add PCIE_LNKCAP2_SLS2SPEED() macro
2020-02-29 3:07 [PATCH v5 0/4] Improve link speed presentation process Bjorn Helgaas
` (2 preceding siblings ...)
2020-02-29 3:07 ` [PATCH v5 3/4] PCI: Use pci_speed_string() for all PCI/PCI-X/PCIe strings Bjorn Helgaas
@ 2020-02-29 3:07 ` Bjorn Helgaas
2020-03-02 23:46 ` [PATCH v5 0/4] Improve link speed presentation process Bjorn Helgaas
4 siblings, 0 replies; 8+ messages in thread
From: Bjorn Helgaas @ 2020-02-29 3:07 UTC (permalink / raw)
To: Yicong Yang; +Cc: Jay Fang, huangdaode, linux-pci, Bjorn Helgaas
From: Yicong Yang <yangyicong@hisilicon.com>
Add PCIE_LNKCAP2_SLS2SPEED macro for transforming raw Link Capabilities 2
values to the pci_bus_speed. This is next to PCIE_SPEED2MBS_ENC() to make
it easier to update both places when adding support for new speeds.
Link: https://lore.kernel.org/r/1581937984-40353-10-git-send-email-yangyicong@hisilicon.com
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/pci.c | 17 ++++-------------
drivers/pci/pci.h | 9 +++++++++
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 421587badecf..e79cccbbdd39 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -5784,19 +5784,10 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
* where only 2.5 GT/s and 5.0 GT/s speeds were defined.
*/
pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
- if (lnkcap2) { /* PCIe r3.0-compliant */
- if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB)
- return PCIE_SPEED_32_0GT;
- else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
- return PCIE_SPEED_16_0GT;
- else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
- return PCIE_SPEED_8_0GT;
- else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
- return PCIE_SPEED_5_0GT;
- else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
- return PCIE_SPEED_2_5GT;
- return PCI_SPEED_UNKNOWN;
- }
+
+ /* PCIe r3.0-compliant */
+ if (lnkcap2)
+ return PCIE_LNKCAP2_SLS2SPEED(lnkcap2);
pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 01f5d7f449a5..75d027ecfbcd 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -292,6 +292,15 @@ void pci_disable_bridge_window(struct pci_dev *dev);
struct pci_bus *pci_bus_get(struct pci_bus *bus);
void pci_bus_put(struct pci_bus *bus);
+/* PCIe link information from Link Capabilities 2 */
+#define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
+ ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
+ (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
+ (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
+ (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
+ (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
+ PCI_SPEED_UNKNOWN)
+
/* PCIe speed to Mb/s reduced by encoding overhead */
#define PCIE_SPEED2MBS_ENC(speed) \
((speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
--
2.25.0.265.gbab2e86ba0-goog
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v5 0/4] Improve link speed presentation process
2020-02-29 3:07 [PATCH v5 0/4] Improve link speed presentation process Bjorn Helgaas
` (3 preceding siblings ...)
2020-02-29 3:07 ` [PATCH v5 4/4] PCI: Add PCIE_LNKCAP2_SLS2SPEED() macro Bjorn Helgaas
@ 2020-03-02 23:46 ` Bjorn Helgaas
4 siblings, 0 replies; 8+ messages in thread
From: Bjorn Helgaas @ 2020-03-02 23:46 UTC (permalink / raw)
To: Yicong Yang; +Cc: Jay Fang, huangdaode, linux-pci
On Fri, Feb 28, 2020 at 09:07:02PM -0600, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <bhelgaas@google.com>
>
> Here's my proposal for merging this series.
>
> The main difference from v4 is that this adds a pci_speed_string()
> interface instead of making the table public and uses that everywhere
> instead of PCI_SPEED2STR().
>
>
> v4: https://lore.kernel.org/r/1581937984-40353-1-git-send-email-yangyicong@hisilicon.com
>
> Bjorn Helgaas (2):
> PCI: Add pci_speed_string()
> PCI: Use pci_speed_string() for all PCI/PCI-X/PCIe strings
>
> Yicong Yang (2):
> PCI: Add 32 GT/s decoding in some macros
> PCI: Add PCIE_LNKCAP2_SLS2SPEED() macro
>
> drivers/pci/controller/pcie-brcmstb.c | 3 +--
> drivers/pci/pci-sysfs.c | 27 ++++---------------
> drivers/pci/pci.c | 23 +++++-----------
> drivers/pci/pci.h | 19 ++++++++------
> drivers/pci/probe.c | 38 +++++++++++++++++++++++++++
> drivers/pci/slot.c | 38 +--------------------------
> include/linux/pci.h | 2 +-
> 7 files changed, 64 insertions(+), 86 deletions(-)
Applied to pci/enumeration for v5.7.
^ permalink raw reply [flat|nested] 8+ messages in thread