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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Manasi Navare <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org, Kazlauskas@freedesktop.org,
	dri-devel@lists.freedesktop.org,
	Nicholas <Nicholas.Kazlauskas@amd.com>
Subject: Re: [PATCH v3] drm/dp: Add function to parse EDID descriptors for adaptive sync limits
Date: Wed, 4 Mar 2020 20:31:23 +0200	[thread overview]
Message-ID: <20200304183123.GG13686@intel.com> (raw)
In-Reply-To: <20200304173606.GA19311@intel.com>

On Wed, Mar 04, 2020 at 09:36:06AM -0800, Manasi Navare wrote:
> On Tue, Mar 03, 2020 at 03:42:12PM +0200, Ville Syrjälä wrote:
> > On Mon, Mar 02, 2020 at 04:08:59PM -0800, Manasi Navare wrote:
> > > Adaptive Sync is a VESA feature so add a DRM core helper to parse
> > > the EDID's detailed descritors to obtain the adaptive sync monitor range.
> > > Store this info as part fo drm_display_info so it can be used
> > > across all drivers.
> > > This part of the code is stripped out of amdgpu's function
> > > amdgpu_dm_update_freesync_caps() to make it generic and be used
> > > across all DRM drivers
> > > 
> > > v3:
> > > * Remove the edid parsing restriction for just DP (Nicholas)
> > > * Use drm_for_each_detailed_block (Ville)
> > > * Make the drm_get_adaptive_sync_range function static (Harry, Jani)
> > > v2:
> > > * Change vmin and vmax to use u8 (Ville)
> > > * Dont store pixel clock since that is just a max dotclock
> > > and not related to VRR mode (Manasi)
> > > 
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Cc: Harry Wentland <harry.wentland@amd.com>
> > > Cc: Clinton A Taylor <clinton.a.taylor@intel.com>
> > > Cc: Kazlauskas, Nicholas <Nicholas.Kazlauskas@amd.com>
> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > ---
> > >  drivers/gpu/drm/drm_edid.c  | 44 +++++++++++++++++++++++++++++++++++++
> > >  include/drm/drm_connector.h | 22 +++++++++++++++++++
> > >  2 files changed, 66 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > > index ad41764a4ebe..e3f152180b6b 100644
> > > --- a/drivers/gpu/drm/drm_edid.c
> > > +++ b/drivers/gpu/drm/drm_edid.c
> > > @@ -4938,6 +4938,47 @@ static void drm_parse_cea_ext(struct drm_connector *connector,
> > >  	}
> > >  }
> > >  
> > > +static
> > > +void get_adaptive_sync_range(struct detailed_timing *timing,
> > > +			     void *info_adaptive_sync)
> > > +{
> > > +	struct drm_adaptive_sync_info *adaptive_sync = info_adaptive_sync;
> > > +	const struct detailed_non_pixel *data = &timing->data.other_data;
> > > +	const struct detailed_data_monitor_range *range = &data->data.range;
> > > +
> > > +	if (data->type != EDID_DETAIL_MONITOR_RANGE)a
> > 
> > is_display_descriptor()
> 
> Will change to use is_display_descriptor()
> 
> > 
> > > +		return;
> > > +
> > > +	/*
> > > +	 * Check for flag range limits only. If flag == 1 then
> > > +	 * no additional timing information provided.
> > > +	 * Default GTF, GTF Secondary curve and CVT are not
> > > +	 * supported
> > > +	 */
> > > +	if (range->flags != 1)
> > 
> > Pls name the flags.
> 
> I dont see that we have any enum with the flag names, do you want me to define them looking
> at EDID spec?

What else?

-- 
Ville Syrjälä
Intel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

WARNING: multiple messages have this Message-ID (diff)
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Manasi Navare <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org, Kazlauskas@freedesktop.org,
	dri-devel@lists.freedesktop.org,
	Nicholas <Nicholas.Kazlauskas@amd.com>
Subject: Re: [Intel-gfx] [PATCH v3] drm/dp: Add function to parse EDID descriptors for adaptive sync limits
Date: Wed, 4 Mar 2020 20:31:23 +0200	[thread overview]
Message-ID: <20200304183123.GG13686@intel.com> (raw)
In-Reply-To: <20200304173606.GA19311@intel.com>

On Wed, Mar 04, 2020 at 09:36:06AM -0800, Manasi Navare wrote:
> On Tue, Mar 03, 2020 at 03:42:12PM +0200, Ville Syrjälä wrote:
> > On Mon, Mar 02, 2020 at 04:08:59PM -0800, Manasi Navare wrote:
> > > Adaptive Sync is a VESA feature so add a DRM core helper to parse
> > > the EDID's detailed descritors to obtain the adaptive sync monitor range.
> > > Store this info as part fo drm_display_info so it can be used
> > > across all drivers.
> > > This part of the code is stripped out of amdgpu's function
> > > amdgpu_dm_update_freesync_caps() to make it generic and be used
> > > across all DRM drivers
> > > 
> > > v3:
> > > * Remove the edid parsing restriction for just DP (Nicholas)
> > > * Use drm_for_each_detailed_block (Ville)
> > > * Make the drm_get_adaptive_sync_range function static (Harry, Jani)
> > > v2:
> > > * Change vmin and vmax to use u8 (Ville)
> > > * Dont store pixel clock since that is just a max dotclock
> > > and not related to VRR mode (Manasi)
> > > 
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Cc: Harry Wentland <harry.wentland@amd.com>
> > > Cc: Clinton A Taylor <clinton.a.taylor@intel.com>
> > > Cc: Kazlauskas, Nicholas <Nicholas.Kazlauskas@amd.com>
> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > ---
> > >  drivers/gpu/drm/drm_edid.c  | 44 +++++++++++++++++++++++++++++++++++++
> > >  include/drm/drm_connector.h | 22 +++++++++++++++++++
> > >  2 files changed, 66 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > > index ad41764a4ebe..e3f152180b6b 100644
> > > --- a/drivers/gpu/drm/drm_edid.c
> > > +++ b/drivers/gpu/drm/drm_edid.c
> > > @@ -4938,6 +4938,47 @@ static void drm_parse_cea_ext(struct drm_connector *connector,
> > >  	}
> > >  }
> > >  
> > > +static
> > > +void get_adaptive_sync_range(struct detailed_timing *timing,
> > > +			     void *info_adaptive_sync)
> > > +{
> > > +	struct drm_adaptive_sync_info *adaptive_sync = info_adaptive_sync;
> > > +	const struct detailed_non_pixel *data = &timing->data.other_data;
> > > +	const struct detailed_data_monitor_range *range = &data->data.range;
> > > +
> > > +	if (data->type != EDID_DETAIL_MONITOR_RANGE)a
> > 
> > is_display_descriptor()
> 
> Will change to use is_display_descriptor()
> 
> > 
> > > +		return;
> > > +
> > > +	/*
> > > +	 * Check for flag range limits only. If flag == 1 then
> > > +	 * no additional timing information provided.
> > > +	 * Default GTF, GTF Secondary curve and CVT are not
> > > +	 * supported
> > > +	 */
> > > +	if (range->flags != 1)
> > 
> > Pls name the flags.
> 
> I dont see that we have any enum with the flag names, do you want me to define them looking
> at EDID spec?

What else?

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2020-03-04 18:31 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-03  0:08 [PATCH v3] drm/dp: Add function to parse EDID descriptors for adaptive sync limits Manasi Navare
2020-03-03  0:08 ` [Intel-gfx] " Manasi Navare
2020-03-03  1:53 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/dp: Add function to parse EDID descriptors for adaptive sync limits (rev2) Patchwork
2020-03-03  2:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-03-03 13:42 ` [PATCH v3] drm/dp: Add function to parse EDID descriptors for adaptive sync limits Ville Syrjälä
2020-03-03 13:42   ` [Intel-gfx] " Ville Syrjälä
2020-03-04 17:36   ` Manasi Navare
2020-03-04 17:36     ` [Intel-gfx] " Manasi Navare
2020-03-04 18:31     ` Ville Syrjälä [this message]
2020-03-04 18:31       ` Ville Syrjälä
2020-03-03 16:17 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/dp: Add function to parse EDID descriptors for adaptive sync limits (rev2) Patchwork

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