* [Intel-gfx] [PATCH 1/4] drm/i915: Don't check uv_wm in skl_plane_wm_equals()
@ 2020-02-28 20:35 Ville Syrjala
2020-02-28 20:35 ` [Intel-gfx] [PATCH 2/4] drm/i915: Don't check for wm changes until we've compute the wms fully Ville Syrjala
` (5 more replies)
0 siblings, 6 replies; 11+ messages in thread
From: Ville Syrjala @ 2020-02-28 20:35 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The hardware never sees the uv_wm values (apart from
uv_wm.min_ddb_alloc affecting the ddb allocation). Thus there
is no point in comparing uv_wm to determine if we need to
reprogram the watermark registers. So let's check only the
rgb/y watermark in skl_plane_wm_equals(). But let's leave
a comment behind so that the next person reading this doesn't
get as confused as I did when I added this check.
If the ddb allocation ends up changing due to uv_wm
skl_ddb_add_affected_planes() takes care of adding the plane
to the state.
TODO: we should perhaps just eliminate uv_wm from the state
and simply track the min_ddb_alloc for uv instead.
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 345429e5ad45..39299811b650 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5400,8 +5400,12 @@ static bool skl_plane_wm_equals(struct drm_i915_private *dev_priv,
int level, max_level = ilk_wm_max_level(dev_priv);
for (level = 0; level <= max_level; level++) {
- if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level]) ||
- !skl_wm_level_equals(&wm1->uv_wm[level], &wm2->uv_wm[level]))
+ /*
+ * We don't check uv_wm as the hardware doesn't actually
+ * use it. It only gets used for calculating the required
+ * ddb allocation.
+ */
+ if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level]))
return false;
}
--
2.24.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 2/4] drm/i915: Don't check for wm changes until we've compute the wms fully
2020-02-28 20:35 [Intel-gfx] [PATCH 1/4] drm/i915: Don't check uv_wm in skl_plane_wm_equals() Ville Syrjala
@ 2020-02-28 20:35 ` Ville Syrjala
2020-03-04 0:21 ` Souza, Jose
2020-02-28 20:35 ` [Intel-gfx] [PATCH 3/4] drm/i915: Enable transition watermarks for glk Ville Syrjala
` (4 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Ville Syrjala @ 2020-02-28 20:35 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Currently we're comparing the watermarks between the old and new states
before we've fully computed the new watermarks. In particular
skl_build_pipe_wm() will not account for the amount of ddb space we'll
have. That information is only available during skl_compute_ddb()
which will proceed to zero out any watermark level exceeding the
ddb allocation. If we're short on ddb space this will end up
adding the plane to the state due erronously determining that the
watermarks have changed. Fix the problem by deferring
skl_wm_add_affected_planes() until we have the final watermarks
computed.
Noticed this when trying enable transition watermarks on glk.
We now computed the trans_wm as 28, but we only had 14 blocks
of ddb, and thus skl_compute_ddb() ended up disabling the cursor
trans_wm every time. Thus we ended up adding the cursor to every
commit that didn't actually affect the cursor at all.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 39299811b650..a3d76e69caae 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5762,16 +5762,24 @@ skl_compute_wm(struct intel_atomic_state *state)
ret = skl_build_pipe_wm(new_crtc_state);
if (ret)
return ret;
-
- ret = skl_wm_add_affected_planes(state, crtc);
- if (ret)
- return ret;
}
ret = skl_compute_ddb(state);
if (ret)
return ret;
+ /*
+ * skl_compute_ddb() will have adjusted the final watermarks
+ * based on how much ddb is available. Now we can actually
+ * check if the final watermarks changed.
+ */
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ ret = skl_wm_add_affected_planes(state, crtc);
+ if (ret)
+ return ret;
+ }
+
skl_print_wm_changes(state);
return 0;
--
2.24.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 3/4] drm/i915: Enable transition watermarks for glk
2020-02-28 20:35 [Intel-gfx] [PATCH 1/4] drm/i915: Don't check uv_wm in skl_plane_wm_equals() Ville Syrjala
2020-02-28 20:35 ` [Intel-gfx] [PATCH 2/4] drm/i915: Don't check for wm changes until we've compute the wms fully Ville Syrjala
@ 2020-02-28 20:35 ` Ville Syrjala
2020-02-28 20:35 ` [Intel-gfx] [PATCH 4/4] drm/i915: Implement display w/a 1140 for glk/cnl Ville Syrjala
` (3 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Ville Syrjala @ 2020-02-28 20:35 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We are mistakenly skipping transition watermarks on glk. Fix
up the condition for glk, and toss in the w/a name from
the database.
v2: Reorder the ipc enabled vs. platform check to be more sensible
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> #v1
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a3d76e69caae..f7c11b9f2c29 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5120,14 +5120,17 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
const u16 trans_amount = 10; /* This is configurable amount */
u16 wm0_sel_res_b, trans_offset_b, res_blocks;
- /* Transition WM are not recommended by HW team for GEN9 */
- if (INTEL_GEN(dev_priv) <= 9)
- return;
-
/* Transition WM don't make any sense if ipc is disabled */
if (!dev_priv->ipc_enabled)
return;
+ /*
+ * WaDisableTWM:skl,kbl,cfl,bxt
+ * Transition WM are not recommended by HW team for GEN9
+ */
+ if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
+ return;
+
trans_min = 14;
if (INTEL_GEN(dev_priv) >= 11)
trans_min = 4;
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 4/4] drm/i915: Implement display w/a 1140 for glk/cnl
2020-02-28 20:35 [Intel-gfx] [PATCH 1/4] drm/i915: Don't check uv_wm in skl_plane_wm_equals() Ville Syrjala
2020-02-28 20:35 ` [Intel-gfx] [PATCH 2/4] drm/i915: Don't check for wm changes until we've compute the wms fully Ville Syrjala
2020-02-28 20:35 ` [Intel-gfx] [PATCH 3/4] drm/i915: Enable transition watermarks for glk Ville Syrjala
@ 2020-02-28 20:35 ` Ville Syrjala
2020-02-28 21:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Don't check uv_wm in skl_plane_wm_equals() Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Ville Syrjala @ 2020-02-28 20:35 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Display w/a #1140 tells us we have to program the transition
watermark to the minimum value on glk/cnl. Let's do that.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f7c11b9f2c29..04013af1eaf1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5116,8 +5116,7 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
{
struct drm_device *dev = crtc_state->uapi.crtc->dev;
const struct drm_i915_private *dev_priv = to_i915(dev);
- u16 trans_min, trans_y_tile_min;
- const u16 trans_amount = 10; /* This is configurable amount */
+ u16 trans_min, trans_amount, trans_y_tile_min;
u16 wm0_sel_res_b, trans_offset_b, res_blocks;
/* Transition WM don't make any sense if ipc is disabled */
@@ -5131,9 +5130,16 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
return;
- trans_min = 14;
if (INTEL_GEN(dev_priv) >= 11)
trans_min = 4;
+ else
+ trans_min = 14;
+
+ /* Display WA #1140: glk,cnl */
+ if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ trans_amount = 0;
+ else
+ trans_amount = 10; /* This is configurable amount */
trans_offset_b = trans_min + trans_amount;
@@ -5160,7 +5166,6 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
/* WA BUG:1938466 add one block for non y-tile planes */
if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
res_blocks += 1;
-
}
/*
--
2.24.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Don't check uv_wm in skl_plane_wm_equals()
2020-02-28 20:35 [Intel-gfx] [PATCH 1/4] drm/i915: Don't check uv_wm in skl_plane_wm_equals() Ville Syrjala
` (2 preceding siblings ...)
2020-02-28 20:35 ` [Intel-gfx] [PATCH 4/4] drm/i915: Implement display w/a 1140 for glk/cnl Ville Syrjala
@ 2020-02-28 21:27 ` Patchwork
2020-03-01 18:23 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-03-04 0:14 ` [Intel-gfx] [PATCH 1/4] " Souza, Jose
5 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2020-02-28 21:27 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915: Don't check uv_wm in skl_plane_wm_equals()
URL : https://patchwork.freedesktop.org/series/74092/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8033 -> Patchwork_16768
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16768:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_lrc:
- {fi-tgl-dsi}: NOTRUN -> [DMESG-FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/fi-tgl-dsi/igt@i915_selftest@live@gt_lrc.html
Known issues
------------
Here are the changes found in Patchwork_16768 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@active:
- fi-cfl-8109u: [PASS][2] -> [DMESG-FAIL][3] ([i915#666])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/fi-cfl-8109u/igt@i915_selftest@live@active.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/fi-cfl-8109u/igt@i915_selftest@live@active.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [PASS][4] -> [DMESG-WARN][5] ([CI#94] / [i915#402])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-tgl-y: [FAIL][6] ([CI#94]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6700k2: [INCOMPLETE][8] ([i915#151]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/fi-skl-6700k2/igt@i915_pm_rpm@module-reload.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/fi-skl-6700k2/igt@i915_pm_rpm@module-reload.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][10] ([fdo#111407]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][12] ([i915#44]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
* igt@prime_self_import@basic-llseek-bad:
- fi-tgl-y: [DMESG-WARN][14] ([CI#94] / [i915#402]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/fi-tgl-y/igt@prime_self_import@basic-llseek-bad.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/fi-tgl-y/igt@prime_self_import@basic-llseek-bad.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#44]: https://gitlab.freedesktop.org/drm/intel/issues/44
[i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666
Participating hosts (48 -> 41)
------------------------------
Additional (4): fi-kbl-soraka fi-byt-j1900 fi-glk-dsi fi-kbl-7560u
Missing (11): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-snb-2520m fi-ctg-p8600 fi-ivb-3770 fi-bdw-samus fi-byt-clapper fi-skl-6600u fi-snb-2600
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8033 -> Patchwork_16768
CI-20190529: 20190529
CI_DRM_8033: de34c8a09179f693b84174d43855172ec76c30b3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5477: 3fe5828f45fc533ba4d9ee84dbb5aea320ce61bc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16768: bf886daea063a6a886ea297a5500004e12d69692 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
bf886daea063 drm/i915: Implement display w/a 1140 for glk/cnl
c32d3d0a88d0 drm/i915: Enable transition watermarks for glk
1a8724cb6ad6 drm/i915: Don't check for wm changes until we've compute the wms fully
d874557c951e drm/i915: Don't check uv_wm in skl_plane_wm_equals()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/4] drm/i915: Don't check uv_wm in skl_plane_wm_equals()
2020-02-28 20:35 [Intel-gfx] [PATCH 1/4] drm/i915: Don't check uv_wm in skl_plane_wm_equals() Ville Syrjala
` (3 preceding siblings ...)
2020-02-28 21:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Don't check uv_wm in skl_plane_wm_equals() Patchwork
@ 2020-03-01 18:23 ` Patchwork
2020-03-04 0:14 ` [Intel-gfx] [PATCH 1/4] " Souza, Jose
5 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2020-03-01 18:23 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915: Don't check uv_wm in skl_plane_wm_equals()
URL : https://patchwork.freedesktop.org/series/74092/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8033_full -> Patchwork_16768_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16768_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16768_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16768_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@evict:
- shard-iclb: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-iclb7/igt@i915_selftest@live@evict.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-iclb3/igt@i915_selftest@live@evict.html
Known issues
------------
Here are the changes found in Patchwork_16768_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@engines-mixed-process@bcs0:
- shard-glk: [PASS][3] -> [INCOMPLETE][4] ([i915#1197] / [i915#1239] / [i915#58] / [k.org#198133])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-glk2/igt@gem_ctx_persistence@engines-mixed-process@bcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-glk3/igt@gem_ctx_persistence@engines-mixed-process@bcs0.html
* igt@gem_ctx_persistence@engines-mixed-process@rcs0:
- shard-glk: [PASS][5] -> [FAIL][6] ([i915#679])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-glk2/igt@gem_ctx_persistence@engines-mixed-process@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-glk3/igt@gem_ctx_persistence@engines-mixed-process@rcs0.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#110854])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-iclb2/igt@gem_exec_balancer@smoke.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-iclb3/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_schedule@pi-shared-iova-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([i915#677]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-iclb6/igt@gem_exec_schedule@pi-shared-iova-bsd.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-iclb1/igt@gem_exec_schedule@pi-shared-iova-bsd.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +5 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-iclb5/igt@gem_exec_schedule@preemptive-hang-bsd.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +6 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-kbl4/igt@gem_exec_suspend@basic-s3.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-kbl2/igt@gem_exec_suspend@basic-s3.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-tglb: [PASS][15] -> [FAIL][16] ([i915#644])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-tglb6/igt@gem_ppgtt@flink-and-close-vma-leak.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-tglb6/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#716])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-skl3/igt@gen9_exec_parse@allowed-single.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-skl2/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_rps@reset:
- shard-iclb: [PASS][19] -> [FAIL][20] ([i915#413])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-iclb3/igt@i915_pm_rps@reset.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-iclb4/igt@i915_pm_rps@reset.html
* igt@i915_selftest@live@hangcheck:
- shard-iclb: [PASS][21] -> [INCOMPLETE][22] ([fdo#108569])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-iclb7/igt@i915_selftest@live@hangcheck.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-iclb3/igt@i915_selftest@live@hangcheck.html
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-pipe-a:
- shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#62] / [i915#92]) +22 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-kbl7/igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-pipe-a.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-kbl6/igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-pipe-a.html
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-glk: [PASS][25] -> [FAIL][26] ([i915#407])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-glk8/igt@kms_flip@2x-modeset-vs-vblank-race.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-glk9/igt@kms_flip@2x-modeset-vs-vblank-race.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-hsw: [PASS][27] -> [INCOMPLETE][28] ([i915#61])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-hsw7/igt@kms_flip@flip-vs-suspend-interruptible.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-hsw4/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-apl: [PASS][29] -> [DMESG-WARN][30] ([i915#180])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-apl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-apl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-hsw: [PASS][31] -> [DMESG-FAIL][32] ([IGT#6])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-hsw1/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-hsw5/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][33] -> [FAIL][34] ([fdo#108145] / [i915#265])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-glk: [PASS][35] -> [FAIL][36] ([i915#899])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-glk6/igt@kms_plane_lowres@pipe-a-tiling-y.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-glk9/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][37] -> [SKIP][38] ([fdo#109441]) +2 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][39] -> [FAIL][40] ([i915#31])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-apl1/igt@kms_setmode@basic.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-apl3/igt@kms_setmode@basic.html
* igt@perf_pmu@busy-no-semaphores-vcs1:
- shard-iclb: [PASS][41] -> [SKIP][42] ([fdo#112080]) +6 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-iclb4/igt@perf_pmu@busy-no-semaphores-vcs1.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-iclb6/igt@perf_pmu@busy-no-semaphores-vcs1.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [PASS][43] -> [SKIP][44] ([fdo#109276]) +20 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-iclb2/igt@prime_busy@hang-bsd2.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-iclb6/igt@prime_busy@hang-bsd2.html
#### Possible fixes ####
* igt@gem_exec_schedule@implicit-read-write-bsd1:
- shard-iclb: [SKIP][45] ([fdo#109276] / [i915#677]) -> [PASS][46] +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-iclb8/igt@gem_exec_schedule@implicit-read-write-bsd1.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-iclb2/igt@gem_exec_schedule@implicit-read-write-bsd1.html
* igt@gem_exec_schedule@in-order-bsd:
- shard-iclb: [SKIP][47] ([fdo#112146]) -> [PASS][48] +5 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-iclb4/igt@gem_exec_schedule@in-order-bsd.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-iclb6/igt@gem_exec_schedule@in-order-bsd.html
* igt@gem_exec_schedule@pi-common-bsd:
- shard-iclb: [SKIP][49] ([i915#677]) -> [PASS][50] +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-iclb1/igt@gem_exec_schedule@pi-common-bsd.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-iclb7/igt@gem_exec_schedule@pi-common-bsd.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [SKIP][51] ([fdo#109276]) -> [PASS][52] +18 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd1.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-iclb2/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_exec_whisper@basic-contexts-forked:
- shard-glk: [INCOMPLETE][53] ([i915#58] / [k.org#198133]) -> [PASS][54] +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-glk4/igt@gem_exec_whisper@basic-contexts-forked.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-glk5/igt@gem_exec_whisper@basic-contexts-forked.html
* igt@i915_pm_rps@waitboost:
- shard-iclb: [FAIL][55] ([i915#413]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-iclb8/igt@i915_pm_rps@waitboost.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-iclb2/igt@i915_pm_rps@waitboost.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [FAIL][57] ([i915#79]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: [DMESG-WARN][59] ([i915#180]) -> [PASS][60] +5 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [FAIL][61] ([fdo#108145]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-skl: [DMESG-WARN][63] ([IGT#6]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-skl6/igt@kms_plane_multiple@atomic-pipe-b-tiling-y.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-skl8/igt@kms_plane_multiple@atomic-pipe-b-tiling-y.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][65] ([fdo#109441]) -> [PASS][66] +2 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [DMESG-WARN][67] ([i915#180]) -> [PASS][68] +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-kbl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@perf_pmu@busy-vcs1:
- shard-iclb: [SKIP][69] ([fdo#112080]) -> [PASS][70] +10 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-iclb3/igt@perf_pmu@busy-vcs1.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-iclb4/igt@perf_pmu@busy-vcs1.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [SKIP][71] ([fdo#112080]) -> [FAIL][72] ([IGT#28])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-iclb7/igt@gem_ctx_isolation@vcs1-nonpriv.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@i915_pm_rpm@reg-read-ioctl:
- shard-snb: [INCOMPLETE][73] ([i915#82]) -> [SKIP][74] ([fdo#109271])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-snb6/igt@i915_pm_rpm@reg-read-ioctl.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-snb4/igt@i915_pm_rpm@reg-read-ioctl.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [DMESG-WARN][75] ([i915#180]) -> [DMESG-WARN][76] ([i915#62] / [i915#92])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-kbl3/igt@kms_fbcon_fbt@fbc-suspend.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-kbl6/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [INCOMPLETE][77] ([fdo#103665]) -> [DMESG-WARN][78] ([i915#180])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][79] ([i915#1188]) -> [INCOMPLETE][80] ([i915#198])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8033/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
[IGT#6]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1197]: https://gitlab.freedesktop.org/drm/intel/issues/1197
[i915#1239]: https://gitlab.freedesktop.org/drm/intel/issues/1239
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#407]: https://gitlab.freedesktop.org/drm/intel/issues/407
[i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
[i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8033 -> Patchwork_16768
CI-20190529: 20190529
CI_DRM_8033: de34c8a09179f693b84174d43855172ec76c30b3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5477: 3fe5828f45fc533ba4d9ee84dbb5aea320ce61bc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16768: bf886daea063a6a886ea297a5500004e12d69692 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16768/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 1/4] drm/i915: Don't check uv_wm in skl_plane_wm_equals()
2020-02-28 20:35 [Intel-gfx] [PATCH 1/4] drm/i915: Don't check uv_wm in skl_plane_wm_equals() Ville Syrjala
` (4 preceding siblings ...)
2020-03-01 18:23 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-03-04 0:14 ` Souza, Jose
5 siblings, 0 replies; 11+ messages in thread
From: Souza, Jose @ 2020-03-04 0:14 UTC (permalink / raw)
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
On Fri, 2020-02-28 at 22:35 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The hardware never sees the uv_wm values (apart from
> uv_wm.min_ddb_alloc affecting the ddb allocation). Thus there
> is no point in comparing uv_wm to determine if we need to
> reprogram the watermark registers. So let's check only the
> rgb/y watermark in skl_plane_wm_equals(). But let's leave
> a comment behind so that the next person reading this doesn't
> get as confused as I did when I added this check.
>
> If the ddb allocation ends up changing due to uv_wm
> skl_ddb_add_affected_planes() takes care of adding the plane
> to the state.
>
> TODO: we should perhaps just eliminate uv_wm from the state
> and simply track the min_ddb_alloc for uv instead.
>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 345429e5ad45..39299811b650 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5400,8 +5400,12 @@ static bool skl_plane_wm_equals(struct
> drm_i915_private *dev_priv,
> int level, max_level = ilk_wm_max_level(dev_priv);
>
> for (level = 0; level <= max_level; level++) {
> - if (!skl_wm_level_equals(&wm1->wm[level], &wm2-
> >wm[level]) ||
> - !skl_wm_level_equals(&wm1->uv_wm[level], &wm2-
> >uv_wm[level]))
> + /*
> + * We don't check uv_wm as the hardware doesn't
> actually
> + * use it. It only gets used for calculating the
> required
> + * ddb allocation.
> + */
> + if (!skl_wm_level_equals(&wm1->wm[level], &wm2-
> >wm[level]))
> return false;
> }
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 2/4] drm/i915: Don't check for wm changes until we've compute the wms fully
2020-02-28 20:35 ` [Intel-gfx] [PATCH 2/4] drm/i915: Don't check for wm changes until we've compute the wms fully Ville Syrjala
@ 2020-03-04 0:21 ` Souza, Jose
2020-03-04 11:46 ` Ville Syrjälä
0 siblings, 1 reply; 11+ messages in thread
From: Souza, Jose @ 2020-03-04 0:21 UTC (permalink / raw)
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
On Fri, 2020-02-28 at 22:35 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Currently we're comparing the watermarks between the old and new
> states
> before we've fully computed the new watermarks. In particular
> skl_build_pipe_wm() will not account for the amount of ddb space
> we'll
> have. That information is only available during skl_compute_ddb()
> which will proceed to zero out any watermark level exceeding the
> ddb allocation. If we're short on ddb space this will end up
> adding the plane to the state due erronously determining that the
> watermarks have changed. Fix the problem by deferring
> skl_wm_add_affected_planes() until we have the final watermarks
> computed.
>
> Noticed this when trying enable transition watermarks on glk.
> We now computed the trans_wm as 28, but we only had 14 blocks
> of ddb, and thus skl_compute_ddb() ended up disabling the cursor
> trans_wm every time. Thus we ended up adding the cursor to every
> commit that didn't actually affect the cursor at all.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++----
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 39299811b650..a3d76e69caae 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5762,16 +5762,24 @@ skl_compute_wm(struct intel_atomic_state
> *state)
> ret = skl_build_pipe_wm(new_crtc_state);
> if (ret)
> return ret;
> -
> - ret = skl_wm_add_affected_planes(state, crtc);
> - if (ret)
> - return ret;
> }
>
> ret = skl_compute_ddb(state);
> if (ret)
> return ret;
>
> + /*
> + * skl_compute_ddb() will have adjusted the final watermarks
> + * based on how much ddb is available. Now we can actually
> + * check if the final watermarks changed.
> + */
> + for_each_oldnew_intel_crtc_in_state(state, crtc,
> old_crtc_state,
> + new_crtc_state, i) {
> + ret = skl_wm_add_affected_planes(state, crtc);
> + if (ret)
> + return ret;
> + }
skl_compute_ddb() is already calling skl_wm_add_affected_planes() after
do the ddb allocation for each pipe, so we could remove this chunk,
with that:
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> +
> skl_print_wm_changes(state);
>
> return 0;
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 2/4] drm/i915: Don't check for wm changes until we've compute the wms fully
2020-03-04 0:21 ` Souza, Jose
@ 2020-03-04 11:46 ` Ville Syrjälä
2020-03-04 23:25 ` Souza, Jose
0 siblings, 1 reply; 11+ messages in thread
From: Ville Syrjälä @ 2020-03-04 11:46 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx@lists.freedesktop.org
On Wed, Mar 04, 2020 at 12:21:01AM +0000, Souza, Jose wrote:
> On Fri, 2020-02-28 at 22:35 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Currently we're comparing the watermarks between the old and new
> > states
> > before we've fully computed the new watermarks. In particular
> > skl_build_pipe_wm() will not account for the amount of ddb space
> > we'll
> > have. That information is only available during skl_compute_ddb()
> > which will proceed to zero out any watermark level exceeding the
> > ddb allocation. If we're short on ddb space this will end up
> > adding the plane to the state due erronously determining that the
> > watermarks have changed. Fix the problem by deferring
> > skl_wm_add_affected_planes() until we have the final watermarks
> > computed.
> >
> > Noticed this when trying enable transition watermarks on glk.
> > We now computed the trans_wm as 28, but we only had 14 blocks
> > of ddb, and thus skl_compute_ddb() ended up disabling the cursor
> > trans_wm every time. Thus we ended up adding the cursor to every
> > commit that didn't actually affect the cursor at all.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++----
> > 1 file changed, 12 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 39299811b650..a3d76e69caae 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5762,16 +5762,24 @@ skl_compute_wm(struct intel_atomic_state
> > *state)
> > ret = skl_build_pipe_wm(new_crtc_state);
> > if (ret)
> > return ret;
> > -
> > - ret = skl_wm_add_affected_planes(state, crtc);
> > - if (ret)
> > - return ret;
> > }
> >
> > ret = skl_compute_ddb(state);
> > if (ret)
> > return ret;
> >
> > + /*
> > + * skl_compute_ddb() will have adjusted the final watermarks
> > + * based on how much ddb is available. Now we can actually
> > + * check if the final watermarks changed.
> > + */
> > + for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state,
> > + new_crtc_state, i) {
> > + ret = skl_wm_add_affected_planes(state, crtc);
> > + if (ret)
> > + return ret;
> > + }
>
> skl_compute_ddb() is already calling skl_wm_add_affected_planes() after
> do the ddb allocation for each pipe, so we could remove this chunk,
skl_compute_ddb() calls skl_*ddb*_add_affected_planes(), which is a
different thing.
> with that:
>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> > +
> > skl_print_wm_changes(state);
> >
> > return 0;
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 2/4] drm/i915: Don't check for wm changes until we've compute the wms fully
2020-03-04 11:46 ` Ville Syrjälä
@ 2020-03-04 23:25 ` Souza, Jose
2020-03-05 13:55 ` Ville Syrjälä
0 siblings, 1 reply; 11+ messages in thread
From: Souza, Jose @ 2020-03-04 23:25 UTC (permalink / raw)
To: ville.syrjala@linux.intel.com; +Cc: intel-gfx@lists.freedesktop.org
On Wed, 2020-03-04 at 13:46 +0200, Ville Syrjälä wrote:
> On Wed, Mar 04, 2020 at 12:21:01AM +0000, Souza, Jose wrote:
> > On Fri, 2020-02-28 at 22:35 +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Currently we're comparing the watermarks between the old and new
> > > states
> > > before we've fully computed the new watermarks. In particular
> > > skl_build_pipe_wm() will not account for the amount of ddb space
> > > we'll
> > > have. That information is only available during skl_compute_ddb()
> > > which will proceed to zero out any watermark level exceeding the
> > > ddb allocation. If we're short on ddb space this will end up
> > > adding the plane to the state due erronously determining that the
> > > watermarks have changed. Fix the problem by deferring
> > > skl_wm_add_affected_planes() until we have the final watermarks
> > > computed.
> > >
> > > Noticed this when trying enable transition watermarks on glk.
> > > We now computed the trans_wm as 28, but we only had 14 blocks
> > > of ddb, and thus skl_compute_ddb() ended up disabling the cursor
> > > trans_wm every time. Thus we ended up adding the cursor to every
> > > commit that didn't actually affect the cursor at all.
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++----
> > > 1 file changed, 12 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > b/drivers/gpu/drm/i915/intel_pm.c
> > > index 39299811b650..a3d76e69caae 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -5762,16 +5762,24 @@ skl_compute_wm(struct intel_atomic_state
> > > *state)
> > > ret = skl_build_pipe_wm(new_crtc_state);
> > > if (ret)
> > > return ret;
> > > -
> > > - ret = skl_wm_add_affected_planes(state, crtc);
> > > - if (ret)
> > > - return ret;
> > > }
> > >
> > > ret = skl_compute_ddb(state);
> > > if (ret)
> > > return ret;
> > >
> > > + /*
> > > + * skl_compute_ddb() will have adjusted the final watermarks
> > > + * based on how much ddb is available. Now we can actually
> > > + * check if the final watermarks changed.
> > > + */
> > > + for_each_oldnew_intel_crtc_in_state(state, crtc,
> > > old_crtc_state,
> > > + new_crtc_state, i) {
> > > + ret = skl_wm_add_affected_planes(state, crtc);
> > > + if (ret)
> > > + return ret;
> > > + }
> >
> > skl_compute_ddb() is already calling skl_wm_add_affected_planes()
> > after
> > do the ddb allocation for each pipe, so we could remove this chunk,
>
> skl_compute_ddb() calls skl_*ddb*_add_affected_planes(), which is a
> different thing..
Thanks
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> > with that:
> >
> > Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> >
> > > +
> > > skl_print_wm_changes(state);
> > >
> > > return 0;
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 2/4] drm/i915: Don't check for wm changes until we've compute the wms fully
2020-03-04 23:25 ` Souza, Jose
@ 2020-03-05 13:55 ` Ville Syrjälä
0 siblings, 0 replies; 11+ messages in thread
From: Ville Syrjälä @ 2020-03-05 13:55 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx@lists.freedesktop.org
On Wed, Mar 04, 2020 at 11:25:42PM +0000, Souza, Jose wrote:
> On Wed, 2020-03-04 at 13:46 +0200, Ville Syrjälä wrote:
> > On Wed, Mar 04, 2020 at 12:21:01AM +0000, Souza, Jose wrote:
> > > On Fri, 2020-02-28 at 22:35 +0200, Ville Syrjala wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > >
> > > > Currently we're comparing the watermarks between the old and new
> > > > states
> > > > before we've fully computed the new watermarks. In particular
> > > > skl_build_pipe_wm() will not account for the amount of ddb space
> > > > we'll
> > > > have. That information is only available during skl_compute_ddb()
> > > > which will proceed to zero out any watermark level exceeding the
> > > > ddb allocation. If we're short on ddb space this will end up
> > > > adding the plane to the state due erronously determining that the
> > > > watermarks have changed. Fix the problem by deferring
> > > > skl_wm_add_affected_planes() until we have the final watermarks
> > > > computed.
> > > >
> > > > Noticed this when trying enable transition watermarks on glk.
> > > > We now computed the trans_wm as 28, but we only had 14 blocks
> > > > of ddb, and thus skl_compute_ddb() ended up disabling the cursor
> > > > trans_wm every time. Thus we ended up adding the cursor to every
> > > > commit that didn't actually affect the cursor at all.
> > > >
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++----
> > > > 1 file changed, 12 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > > b/drivers/gpu/drm/i915/intel_pm.c
> > > > index 39299811b650..a3d76e69caae 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > @@ -5762,16 +5762,24 @@ skl_compute_wm(struct intel_atomic_state
> > > > *state)
> > > > ret = skl_build_pipe_wm(new_crtc_state);
> > > > if (ret)
> > > > return ret;
> > > > -
> > > > - ret = skl_wm_add_affected_planes(state, crtc);
> > > > - if (ret)
> > > > - return ret;
> > > > }
> > > >
> > > > ret = skl_compute_ddb(state);
> > > > if (ret)
> > > > return ret;
> > > >
> > > > + /*
> > > > + * skl_compute_ddb() will have adjusted the final watermarks
> > > > + * based on how much ddb is available. Now we can actually
> > > > + * check if the final watermarks changed.
> > > > + */
> > > > + for_each_oldnew_intel_crtc_in_state(state, crtc,
> > > > old_crtc_state,
> > > > + new_crtc_state, i) {
> > > > + ret = skl_wm_add_affected_planes(state, crtc);
> > > > + if (ret)
> > > > + return ret;
> > > > + }
> > >
> > > skl_compute_ddb() is already calling skl_wm_add_affected_planes()
> > > after
> > > do the ddb allocation for each pipe, so we could remove this chunk,
> >
> > skl_compute_ddb() calls skl_*ddb*_add_affected_planes(), which is a
> > different thing..
>
> Thanks
No, thank you for the review. Series pushed to dinq.
>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> >
> > > with that:
> > >
> > > Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> > >
> > > > +
> > > > skl_print_wm_changes(state);
> > > >
> > > > return 0;
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-03-05 13:55 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-02-28 20:35 [Intel-gfx] [PATCH 1/4] drm/i915: Don't check uv_wm in skl_plane_wm_equals() Ville Syrjala
2020-02-28 20:35 ` [Intel-gfx] [PATCH 2/4] drm/i915: Don't check for wm changes until we've compute the wms fully Ville Syrjala
2020-03-04 0:21 ` Souza, Jose
2020-03-04 11:46 ` Ville Syrjälä
2020-03-04 23:25 ` Souza, Jose
2020-03-05 13:55 ` Ville Syrjälä
2020-02-28 20:35 ` [Intel-gfx] [PATCH 3/4] drm/i915: Enable transition watermarks for glk Ville Syrjala
2020-02-28 20:35 ` [Intel-gfx] [PATCH 4/4] drm/i915: Implement display w/a 1140 for glk/cnl Ville Syrjala
2020-02-28 21:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Don't check uv_wm in skl_plane_wm_equals() Patchwork
2020-03-01 18:23 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-03-04 0:14 ` [Intel-gfx] [PATCH 1/4] " Souza, Jose
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