* [PATCH v2 1/6] dt-bindings: syscon: Add TI's J721E specific compatible string
2020-03-03 10:17 [PATCH v2 0/6] arm64: ti: k3-j721e: Add SERDES PHY and USB3.0 support Roger Quadros
@ 2020-03-03 10:17 ` Roger Quadros
2020-03-03 10:17 ` [PATCH v2 2/6] arm64: dts: ti: k3-j721e-main: Add WIZ and SERDES PHY nodes Roger Quadros
` (4 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Roger Quadros @ 2020-03-03 10:17 UTC (permalink / raw)
To: t-kristo; +Cc: robh, kishon, nm, nsekhar, vigneshr, devicetree, linux-kernel
From: Kishon Vijay Abraham I <kishon@ti.com>
Add TI's J721E SoC specific compatible string.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index 39375e4313d2..f9aac75d423a 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -38,6 +38,7 @@ properties:
- allwinner,sun8i-h3-system-controller
- allwinner,sun8i-v3s-system-controller
- allwinner,sun50i-a64-system-controller
+ - ti,j721e-system-controller
- const: syscon
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 2/6] arm64: dts: ti: k3-j721e-main: Add WIZ and SERDES PHY nodes
2020-03-03 10:17 [PATCH v2 0/6] arm64: ti: k3-j721e: Add SERDES PHY and USB3.0 support Roger Quadros
2020-03-03 10:17 ` [PATCH v2 1/6] dt-bindings: syscon: Add TI's J721E specific compatible string Roger Quadros
@ 2020-03-03 10:17 ` Roger Quadros
2020-03-03 10:17 ` [PATCH v2 3/6] arm64: dts: ti: k3-j721e-main: Add serdes_ln_ctrl node to select SERDES lane mux Roger Quadros
` (3 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Roger Quadros @ 2020-03-03 10:17 UTC (permalink / raw)
To: t-kristo
Cc: robh, kishon, nm, nsekhar, vigneshr, devicetree, linux-kernel,
Roger Quadros
From: Kishon Vijay Abraham I <kishon@ti.com>
Add DT nodes for all instances of WIZ and SERDES modules.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 241 ++++++++++++++++++++++
1 file changed, 241 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 0b9d14b838a1..cbaadee5bfdc 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -4,6 +4,7 @@
*
* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
*/
+#include <dt-bindings/phy/phy.h>
&cbass_main {
msmc_ram: sram@70000000 {
@@ -265,6 +266,246 @@
pinctrl-single,function-mask = <0xffffffff>;
};
+ dummy_cmn_refclk: dummy-cmn-refclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
+
+ dummy_cmn_refclk1: dummy-cmn-refclk1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
+
+ serdes_wiz0: wiz@5000000 {
+ compatible = "ti,j721e-wiz-16g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
+ assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
+ num-lanes = <2>;
+ #reset-cells = <1>;
+ ranges = <0x5000000 0x0 0x5000000 0x10000>;
+
+ wiz0_pll0_refclk: pll0-refclk {
+ clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_pll0_refclk>;
+ assigned-clock-parents = <&k3_clks 292 11>;
+ };
+
+ wiz0_pll1_refclk: pll1-refclk {
+ clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_pll1_refclk>;
+ assigned-clock-parents = <&k3_clks 292 0>;
+ };
+
+ wiz0_refclk_dig: refclk-dig {
+ clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_refclk_dig>;
+ assigned-clock-parents = <&k3_clks 292 11>;
+ };
+
+ wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
+ clocks = <&wiz0_refclk_dig>;
+ #clock-cells = <0>;
+ };
+
+ wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
+ clocks = <&wiz0_pll1_refclk>;
+ #clock-cells = <0>;
+ };
+
+ serdes0: serdes@5000000 {
+ compatible = "ti,sierra-phy-t0";
+ reg-names = "serdes";
+ reg = <0x5000000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = <&serdes_wiz0 0>;
+ reset-names = "sierra_reset";
+ clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ };
+ };
+
+ serdes_wiz1: wiz@5010000 {
+ compatible = "ti,j721e-wiz-16g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
+ assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
+ num-lanes = <2>;
+ #reset-cells = <1>;
+ ranges = <0x5010000 0x0 0x5010000 0x10000>;
+
+ wiz1_pll0_refclk: pll0-refclk {
+ clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz1_pll0_refclk>;
+ assigned-clock-parents = <&k3_clks 293 13>;
+ };
+
+ wiz1_pll1_refclk: pll1-refclk {
+ clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz1_pll1_refclk>;
+ assigned-clock-parents = <&k3_clks 293 0>;
+ };
+
+ wiz1_refclk_dig: refclk-dig {
+ clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz1_refclk_dig>;
+ assigned-clock-parents = <&k3_clks 293 13>;
+ };
+
+ wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{
+ clocks = <&wiz1_refclk_dig>;
+ #clock-cells = <0>;
+ };
+
+ wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
+ clocks = <&wiz1_pll1_refclk>;
+ #clock-cells = <0>;
+ };
+
+ serdes1: serdes@5010000 {
+ compatible = "ti,sierra-phy-t0";
+ reg-names = "serdes";
+ reg = <0x5010000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = <&serdes_wiz1 0>;
+ reset-names = "sierra_reset";
+ clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ };
+ };
+
+ serdes_wiz2: wiz@5020000 {
+ compatible = "ti,j721e-wiz-16g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
+ assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
+ num-lanes = <2>;
+ #reset-cells = <1>;
+ ranges = <0x5020000 0x0 0x5020000 0x10000>;
+
+ wiz2_pll0_refclk: pll0-refclk {
+ clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz2_pll0_refclk>;
+ assigned-clock-parents = <&k3_clks 294 11>;
+ };
+
+ wiz2_pll1_refclk: pll1-refclk {
+ clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz2_pll1_refclk>;
+ assigned-clock-parents = <&k3_clks 294 0>;
+ };
+
+ wiz2_refclk_dig: refclk-dig {
+ clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz2_refclk_dig>;
+ assigned-clock-parents = <&k3_clks 294 11>;
+ };
+
+ wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
+ clocks = <&wiz2_refclk_dig>;
+ #clock-cells = <0>;
+ };
+
+ wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
+ clocks = <&wiz2_pll1_refclk>;
+ #clock-cells = <0>;
+ };
+
+ serdes2: serdes@5020000 {
+ compatible = "ti,sierra-phy-t0";
+ reg-names = "serdes";
+ reg = <0x5020000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = <&serdes_wiz2 0>;
+ reset-names = "sierra_reset";
+ clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ };
+ };
+
+ serdes_wiz3: wiz@5030000 {
+ compatible = "ti,j721e-wiz-16g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
+ assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
+ num-lanes = <2>;
+ #reset-cells = <1>;
+ ranges = <0x5030000 0x0 0x5030000 0x10000>;
+
+ wiz3_pll0_refclk: pll0-refclk {
+ clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz3_pll0_refclk>;
+ assigned-clock-parents = <&k3_clks 295 9>;
+ };
+
+ wiz3_pll1_refclk: pll1-refclk {
+ clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz3_pll1_refclk>;
+ assigned-clock-parents = <&k3_clks 295 0>;
+ };
+
+ wiz3_refclk_dig: refclk-dig {
+ clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz3_refclk_dig>;
+ assigned-clock-parents = <&k3_clks 295 9>;
+ };
+
+ wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
+ clocks = <&wiz3_refclk_dig>;
+ #clock-cells = <0>;
+ };
+
+ wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
+ clocks = <&wiz3_pll1_refclk>;
+ #clock-cells = <0>;
+ };
+
+ serdes3: serdes@5030000 {
+ compatible = "ti,sierra-phy-t0";
+ reg-names = "serdes";
+ reg = <0x5030000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = <&serdes_wiz3 0>;
+ reset-names = "sierra_reset";
+ clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ };
+ };
+
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 3/6] arm64: dts: ti: k3-j721e-main: Add serdes_ln_ctrl node to select SERDES lane mux
2020-03-03 10:17 [PATCH v2 0/6] arm64: ti: k3-j721e: Add SERDES PHY and USB3.0 support Roger Quadros
2020-03-03 10:17 ` [PATCH v2 1/6] dt-bindings: syscon: Add TI's J721E specific compatible string Roger Quadros
2020-03-03 10:17 ` [PATCH v2 2/6] arm64: dts: ti: k3-j721e-main: Add WIZ and SERDES PHY nodes Roger Quadros
@ 2020-03-03 10:17 ` Roger Quadros
2020-03-10 21:09 ` Rob Herring
2020-03-03 10:17 ` [PATCH v2 4/6] arm64: dts: ti: k3-j721e-main.dtsi: Add USB to SERDES MUX Roger Quadros
` (2 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Roger Quadros @ 2020-03-03 10:17 UTC (permalink / raw)
To: t-kristo
Cc: robh, kishon, nm, nsekhar, vigneshr, devicetree, linux-kernel,
Roger Quadros
From: Kishon Vijay Abraham I <kishon@ti.com>
Add serdes_ln_ctrl node used for selecting SERDES lane mux.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 27 ++++++++++++
include/dt-bindings/mux/mux-j721e-wiz.h | 53 +++++++++++++++++++++++
2 files changed, 80 insertions(+)
create mode 100644 include/dt-bindings/mux/mux-j721e-wiz.h
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index cbaadee5bfdc..c5d54af37e91 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -5,6 +5,8 @@
* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
*/
#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/mux/mux.h>
+#include <dt-bindings/mux/mux-j721e-wiz.h>
&cbass_main {
msmc_ram: sram@70000000 {
@@ -19,6 +21,31 @@
};
};
+ scm_conf: scm-conf@100000 {
+ compatible = "syscon", "simple-mfd", "ti,j721e-system-controller";
+ reg = <0 0x00100000 0 0x1c000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x00100000 0x1c000>;
+
+ serdes_ln_ctrl: serdes-ln-ctrl@4080 {
+ compatible = "mmio-mux";
+ reg = <0x00004080 0x50>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
+ <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
+ <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
+ <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
+ <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
+ /* SERDES4 lane0/1/2/3 select */
+ idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
+ <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
+ <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
+ <MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
+ <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
+ };
+ };
+
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
diff --git a/include/dt-bindings/mux/mux-j721e-wiz.h b/include/dt-bindings/mux/mux-j721e-wiz.h
new file mode 100644
index 000000000000..fd1c4ea9fc7f
--- /dev/null
+++ b/include/dt-bindings/mux/mux-j721e-wiz.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for J721E WIZ.
+ */
+
+#ifndef _DT_BINDINGS_J721E_WIZ
+#define _DT_BINDINGS_J721E_WIZ
+
+#define SERDES0_LANE0_QSGMII_LANE1 0x0
+#define SERDES0_LANE0_PCIE0_LANE0 0x1
+#define SERDES0_LANE0_USB3_0_SWAP 0x2
+
+#define SERDES0_LANE1_QSGMII_LANE2 0x0
+#define SERDES0_LANE1_PCIE0_LANE1 0x1
+#define SERDES0_LANE1_USB3_0 0x2
+
+#define SERDES1_LANE0_QSGMII_LANE3 0x0
+#define SERDES1_LANE0_PCIE1_LANE0 0x1
+#define SERDES1_LANE0_USB3_1_SWAP 0x2
+#define SERDES1_LANE0_SGMII_LANE0 0x3
+
+#define SERDES1_LANE1_QSGMII_LANE4 0x0
+#define SERDES1_LANE1_PCIE1_LANE1 0x1
+#define SERDES1_LANE1_USB3_1 0x2
+#define SERDES1_LANE1_SGMII_LANE1 0x3
+
+#define SERDES2_LANE0_PCIE2_LANE0 0x1
+#define SERDES2_LANE0_SGMII_LANE0 0x3
+#define SERDES2_LANE0_USB3_1_SWAP 0x2
+
+#define SERDES2_LANE1_PCIE2_LANE1 0x1
+#define SERDES2_LANE1_USB3_1 0x2
+#define SERDES2_LANE1_SGMII_LANE1 0x3
+
+#define SERDES3_LANE0_PCIE3_LANE0 0x1
+#define SERDES3_LANE0_USB3_0_SWAP 0x2
+
+#define SERDES3_LANE1_PCIE3_LANE1 0x1
+#define SERDES3_LANE1_USB3_0 0x2
+
+#define SERDES4_LANE0_EDP_LANE0 0x0
+#define SERDES4_LANE0_QSGMII_LANE5 0x2
+
+#define SERDES4_LANE1_EDP_LANE1 0x0
+#define SERDES4_LANE1_QSGMII_LANE6 0x2
+
+#define SERDES4_LANE2_EDP_LANE2 0x0
+#define SERDES4_LANE2_QSGMII_LANE7 0x2
+
+#define SERDES4_LANE3_EDP_LANE3 0x0
+#define SERDES4_LANE3_QSGMII_LANE8 0x2
+
+#endif /* _DT_BINDINGS_J721E_WIZ */
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v2 3/6] arm64: dts: ti: k3-j721e-main: Add serdes_ln_ctrl node to select SERDES lane mux
2020-03-03 10:17 ` [PATCH v2 3/6] arm64: dts: ti: k3-j721e-main: Add serdes_ln_ctrl node to select SERDES lane mux Roger Quadros
@ 2020-03-10 21:09 ` Rob Herring
2020-03-19 11:37 ` Kishon Vijay Abraham I
0 siblings, 1 reply; 11+ messages in thread
From: Rob Herring @ 2020-03-10 21:09 UTC (permalink / raw)
To: Roger Quadros
Cc: t-kristo, kishon, nm, nsekhar, vigneshr, devicetree, linux-kernel
On Tue, Mar 03, 2020 at 12:17:19PM +0200, Roger Quadros wrote:
> From: Kishon Vijay Abraham I <kishon@ti.com>
>
> Add serdes_ln_ctrl node used for selecting SERDES lane mux.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 27 ++++++++++++
> include/dt-bindings/mux/mux-j721e-wiz.h | 53 +++++++++++++++++++++++
> 2 files changed, 80 insertions(+)
> create mode 100644 include/dt-bindings/mux/mux-j721e-wiz.h
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> index cbaadee5bfdc..c5d54af37e91 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> @@ -5,6 +5,8 @@
> * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
> */
> #include <dt-bindings/phy/phy.h>
> +#include <dt-bindings/mux/mux.h>
> +#include <dt-bindings/mux/mux-j721e-wiz.h>
>
> &cbass_main {
> msmc_ram: sram@70000000 {
> @@ -19,6 +21,31 @@
> };
> };
>
> + scm_conf: scm-conf@100000 {
> + compatible = "syscon", "simple-mfd", "ti,j721e-system-controller";
Wrong ordering. Most significant first.
> + reg = <0 0x00100000 0 0x1c000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x00100000 0x1c000>;
> +
> + serdes_ln_ctrl: serdes-ln-ctrl@4080 {
Your syscon.yaml change is not valid if you have child nodes. Do a
specific binding for this block.
> + compatible = "mmio-mux";
> + reg = <0x00004080 0x50>;
> + #mux-control-cells = <1>;
> + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
> + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
> + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
> + <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
> + <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
> + /* SERDES4 lane0/1/2/3 select */
> + idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
> + <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
> + <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
> + <MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
> + <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
> + };
> + };
> +
> gic500: interrupt-controller@1800000 {
> compatible = "arm,gic-v3";
> #address-cells = <2>;
> diff --git a/include/dt-bindings/mux/mux-j721e-wiz.h b/include/dt-bindings/mux/mux-j721e-wiz.h
> new file mode 100644
> index 000000000000..fd1c4ea9fc7f
> --- /dev/null
> +++ b/include/dt-bindings/mux/mux-j721e-wiz.h
> @@ -0,0 +1,53 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * This header provides constants for J721E WIZ.
> + */
> +
> +#ifndef _DT_BINDINGS_J721E_WIZ
> +#define _DT_BINDINGS_J721E_WIZ
> +
> +#define SERDES0_LANE0_QSGMII_LANE1 0x0
> +#define SERDES0_LANE0_PCIE0_LANE0 0x1
> +#define SERDES0_LANE0_USB3_0_SWAP 0x2
> +
> +#define SERDES0_LANE1_QSGMII_LANE2 0x0
> +#define SERDES0_LANE1_PCIE0_LANE1 0x1
> +#define SERDES0_LANE1_USB3_0 0x2
> +
> +#define SERDES1_LANE0_QSGMII_LANE3 0x0
> +#define SERDES1_LANE0_PCIE1_LANE0 0x1
> +#define SERDES1_LANE0_USB3_1_SWAP 0x2
> +#define SERDES1_LANE0_SGMII_LANE0 0x3
> +
> +#define SERDES1_LANE1_QSGMII_LANE4 0x0
> +#define SERDES1_LANE1_PCIE1_LANE1 0x1
> +#define SERDES1_LANE1_USB3_1 0x2
> +#define SERDES1_LANE1_SGMII_LANE1 0x3
> +
> +#define SERDES2_LANE0_PCIE2_LANE0 0x1
> +#define SERDES2_LANE0_SGMII_LANE0 0x3
> +#define SERDES2_LANE0_USB3_1_SWAP 0x2
> +
> +#define SERDES2_LANE1_PCIE2_LANE1 0x1
> +#define SERDES2_LANE1_USB3_1 0x2
> +#define SERDES2_LANE1_SGMII_LANE1 0x3
> +
> +#define SERDES3_LANE0_PCIE3_LANE0 0x1
> +#define SERDES3_LANE0_USB3_0_SWAP 0x2
> +
> +#define SERDES3_LANE1_PCIE3_LANE1 0x1
> +#define SERDES3_LANE1_USB3_0 0x2
> +
> +#define SERDES4_LANE0_EDP_LANE0 0x0
> +#define SERDES4_LANE0_QSGMII_LANE5 0x2
> +
> +#define SERDES4_LANE1_EDP_LANE1 0x0
> +#define SERDES4_LANE1_QSGMII_LANE6 0x2
> +
> +#define SERDES4_LANE2_EDP_LANE2 0x0
> +#define SERDES4_LANE2_QSGMII_LANE7 0x2
> +
> +#define SERDES4_LANE3_EDP_LANE3 0x0
> +#define SERDES4_LANE3_QSGMII_LANE8 0x2
> +
> +#endif /* _DT_BINDINGS_J721E_WIZ */
> --
> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
> Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
>
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v2 3/6] arm64: dts: ti: k3-j721e-main: Add serdes_ln_ctrl node to select SERDES lane mux
2020-03-10 21:09 ` Rob Herring
@ 2020-03-19 11:37 ` Kishon Vijay Abraham I
2020-04-23 7:03 ` Roger Quadros
2020-04-24 20:15 ` Rob Herring
0 siblings, 2 replies; 11+ messages in thread
From: Kishon Vijay Abraham I @ 2020-03-19 11:37 UTC (permalink / raw)
To: Rob Herring, Roger Quadros
Cc: t-kristo, nm, nsekhar, vigneshr, devicetree, linux-kernel
Hi Rob,
On 11/03/20 2:39 am, Rob Herring wrote:
> On Tue, Mar 03, 2020 at 12:17:19PM +0200, Roger Quadros wrote:
>> From: Kishon Vijay Abraham I <kishon@ti.com>
>>
>> Add serdes_ln_ctrl node used for selecting SERDES lane mux.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>> ---
>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 27 ++++++++++++
>> include/dt-bindings/mux/mux-j721e-wiz.h | 53 +++++++++++++++++++++++
>> 2 files changed, 80 insertions(+)
>> create mode 100644 include/dt-bindings/mux/mux-j721e-wiz.h
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> index cbaadee5bfdc..c5d54af37e91 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> @@ -5,6 +5,8 @@
>> * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
>> */
>> #include <dt-bindings/phy/phy.h>
>> +#include <dt-bindings/mux/mux.h>
>> +#include <dt-bindings/mux/mux-j721e-wiz.h>
>>
>> &cbass_main {
>> msmc_ram: sram@70000000 {
>> @@ -19,6 +21,31 @@
>> };
>> };
>>
>> + scm_conf: scm-conf@100000 {
>> + compatible = "syscon", "simple-mfd", "ti,j721e-system-controller";
>
> Wrong ordering. Most significant first.
>
>> + reg = <0 0x00100000 0 0x1c000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0x0 0x0 0x00100000 0x1c000>;
>> +
>> + serdes_ln_ctrl: serdes-ln-ctrl@4080 {
>
> Your syscon.yaml change is not valid if you have child nodes. Do a
> specific binding for this block.
Do you mean in addition to having platform specific binding for
scm-conf, I need to have platform specific binding for serdes-ln-ctrl.
Since the driver doesn't do any platform specific stuff, the driver
doesn't have to change. Is that correct?
Thanks
Kishon
>
>> + compatible = "mmio-mux";
>> + reg = <0x00004080 0x50>;
>> + #mux-control-cells = <1>;
>> + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
>> + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
>> + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
>> + <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
>> + <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
>> + /* SERDES4 lane0/1/2/3 select */
>> + idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
>> + <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
>> + <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
>> + <MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
>> + <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
>> + };
>> + };
>> +
>> gic500: interrupt-controller@1800000 {
>> compatible = "arm,gic-v3";
>> #address-cells = <2>;
>> diff --git a/include/dt-bindings/mux/mux-j721e-wiz.h b/include/dt-bindings/mux/mux-j721e-wiz.h
>> new file mode 100644
>> index 000000000000..fd1c4ea9fc7f
>> --- /dev/null
>> +++ b/include/dt-bindings/mux/mux-j721e-wiz.h
>> @@ -0,0 +1,53 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * This header provides constants for J721E WIZ.
>> + */
>> +
>> +#ifndef _DT_BINDINGS_J721E_WIZ
>> +#define _DT_BINDINGS_J721E_WIZ
>> +
>> +#define SERDES0_LANE0_QSGMII_LANE1 0x0
>> +#define SERDES0_LANE0_PCIE0_LANE0 0x1
>> +#define SERDES0_LANE0_USB3_0_SWAP 0x2
>> +
>> +#define SERDES0_LANE1_QSGMII_LANE2 0x0
>> +#define SERDES0_LANE1_PCIE0_LANE1 0x1
>> +#define SERDES0_LANE1_USB3_0 0x2
>> +
>> +#define SERDES1_LANE0_QSGMII_LANE3 0x0
>> +#define SERDES1_LANE0_PCIE1_LANE0 0x1
>> +#define SERDES1_LANE0_USB3_1_SWAP 0x2
>> +#define SERDES1_LANE0_SGMII_LANE0 0x3
>> +
>> +#define SERDES1_LANE1_QSGMII_LANE4 0x0
>> +#define SERDES1_LANE1_PCIE1_LANE1 0x1
>> +#define SERDES1_LANE1_USB3_1 0x2
>> +#define SERDES1_LANE1_SGMII_LANE1 0x3
>> +
>> +#define SERDES2_LANE0_PCIE2_LANE0 0x1
>> +#define SERDES2_LANE0_SGMII_LANE0 0x3
>> +#define SERDES2_LANE0_USB3_1_SWAP 0x2
>> +
>> +#define SERDES2_LANE1_PCIE2_LANE1 0x1
>> +#define SERDES2_LANE1_USB3_1 0x2
>> +#define SERDES2_LANE1_SGMII_LANE1 0x3
>> +
>> +#define SERDES3_LANE0_PCIE3_LANE0 0x1
>> +#define SERDES3_LANE0_USB3_0_SWAP 0x2
>> +
>> +#define SERDES3_LANE1_PCIE3_LANE1 0x1
>> +#define SERDES3_LANE1_USB3_0 0x2
>> +
>> +#define SERDES4_LANE0_EDP_LANE0 0x0
>> +#define SERDES4_LANE0_QSGMII_LANE5 0x2
>> +
>> +#define SERDES4_LANE1_EDP_LANE1 0x0
>> +#define SERDES4_LANE1_QSGMII_LANE6 0x2
>> +
>> +#define SERDES4_LANE2_EDP_LANE2 0x0
>> +#define SERDES4_LANE2_QSGMII_LANE7 0x2
>> +
>> +#define SERDES4_LANE3_EDP_LANE3 0x0
>> +#define SERDES4_LANE3_QSGMII_LANE8 0x2
>> +
>> +#endif /* _DT_BINDINGS_J721E_WIZ */
>> --
>> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
>> Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
>>
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v2 3/6] arm64: dts: ti: k3-j721e-main: Add serdes_ln_ctrl node to select SERDES lane mux
2020-03-19 11:37 ` Kishon Vijay Abraham I
@ 2020-04-23 7:03 ` Roger Quadros
2020-04-24 20:15 ` Rob Herring
1 sibling, 0 replies; 11+ messages in thread
From: Roger Quadros @ 2020-04-23 7:03 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Rob Herring
Cc: t-kristo, nm, nsekhar, vigneshr, devicetree, linux-kernel
Kishon, Rob,
On 19/03/2020 13:37, Kishon Vijay Abraham I wrote:
> Hi Rob,
>
> On 11/03/20 2:39 am, Rob Herring wrote:
>> On Tue, Mar 03, 2020 at 12:17:19PM +0200, Roger Quadros wrote:
>>> From: Kishon Vijay Abraham I <kishon@ti.com>
>>>
>>> Add serdes_ln_ctrl node used for selecting SERDES lane mux.
>>>
>>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>>> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
>>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>>> ---
>>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 27 ++++++++++++
>>> include/dt-bindings/mux/mux-j721e-wiz.h | 53 +++++++++++++++++++++++
>>> 2 files changed, 80 insertions(+)
>>> create mode 100644 include/dt-bindings/mux/mux-j721e-wiz.h
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>> index cbaadee5bfdc..c5d54af37e91 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>> @@ -5,6 +5,8 @@
>>> * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
>>> */
>>> #include <dt-bindings/phy/phy.h>
>>> +#include <dt-bindings/mux/mux.h>
>>> +#include <dt-bindings/mux/mux-j721e-wiz.h>
>>>
>>> &cbass_main {
>>> msmc_ram: sram@70000000 {
>>> @@ -19,6 +21,31 @@
>>> };
>>> };
>>>
>>> + scm_conf: scm-conf@100000 {
>>> + compatible = "syscon", "simple-mfd", "ti,j721e-system-controller";
>>
>> Wrong ordering. Most significant first.
>>
>>> + reg = <0 0x00100000 0 0x1c000>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges = <0x0 0x0 0x00100000 0x1c000>;
>>> +
>>> + serdes_ln_ctrl: serdes-ln-ctrl@4080 {
>>
>> Your syscon.yaml change is not valid if you have child nodes. Do a
>> specific binding for this block.
>
> Do you mean in addition to having platform specific binding for
> scm-conf, I need to have platform specific binding for serdes-ln-ctrl.
>
> Since the driver doesn't do any platform specific stuff, the driver
> doesn't have to change. Is that correct?
>
Any resolution on this?
cheers,
-roger
> Thanks
> Kishon
>>
>>> + compatible = "mmio-mux";
>>> + reg = <0x00004080 0x50>;
>>> + #mux-control-cells = <1>;
>>> + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
>>> + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
>>> + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
>>> + <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
>>> + <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
>>> + /* SERDES4 lane0/1/2/3 select */
>>> + idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
>>> + <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
>>> + <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
>>> + <MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
>>> + <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
>>> + };
>>> + };
>>> +
>>> gic500: interrupt-controller@1800000 {
>>> compatible = "arm,gic-v3";
>>> #address-cells = <2>;
>>> diff --git a/include/dt-bindings/mux/mux-j721e-wiz.h b/include/dt-bindings/mux/mux-j721e-wiz.h
>>> new file mode 100644
>>> index 000000000000..fd1c4ea9fc7f
>>> --- /dev/null
>>> +++ b/include/dt-bindings/mux/mux-j721e-wiz.h
>>> @@ -0,0 +1,53 @@
>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>> +/*
>>> + * This header provides constants for J721E WIZ.
>>> + */
>>> +
>>> +#ifndef _DT_BINDINGS_J721E_WIZ
>>> +#define _DT_BINDINGS_J721E_WIZ
>>> +
>>> +#define SERDES0_LANE0_QSGMII_LANE1 0x0
>>> +#define SERDES0_LANE0_PCIE0_LANE0 0x1
>>> +#define SERDES0_LANE0_USB3_0_SWAP 0x2
>>> +
>>> +#define SERDES0_LANE1_QSGMII_LANE2 0x0
>>> +#define SERDES0_LANE1_PCIE0_LANE1 0x1
>>> +#define SERDES0_LANE1_USB3_0 0x2
>>> +
>>> +#define SERDES1_LANE0_QSGMII_LANE3 0x0
>>> +#define SERDES1_LANE0_PCIE1_LANE0 0x1
>>> +#define SERDES1_LANE0_USB3_1_SWAP 0x2
>>> +#define SERDES1_LANE0_SGMII_LANE0 0x3
>>> +
>>> +#define SERDES1_LANE1_QSGMII_LANE4 0x0
>>> +#define SERDES1_LANE1_PCIE1_LANE1 0x1
>>> +#define SERDES1_LANE1_USB3_1 0x2
>>> +#define SERDES1_LANE1_SGMII_LANE1 0x3
>>> +
>>> +#define SERDES2_LANE0_PCIE2_LANE0 0x1
>>> +#define SERDES2_LANE0_SGMII_LANE0 0x3
>>> +#define SERDES2_LANE0_USB3_1_SWAP 0x2
>>> +
>>> +#define SERDES2_LANE1_PCIE2_LANE1 0x1
>>> +#define SERDES2_LANE1_USB3_1 0x2
>>> +#define SERDES2_LANE1_SGMII_LANE1 0x3
>>> +
>>> +#define SERDES3_LANE0_PCIE3_LANE0 0x1
>>> +#define SERDES3_LANE0_USB3_0_SWAP 0x2
>>> +
>>> +#define SERDES3_LANE1_PCIE3_LANE1 0x1
>>> +#define SERDES3_LANE1_USB3_0 0x2
>>> +
>>> +#define SERDES4_LANE0_EDP_LANE0 0x0
>>> +#define SERDES4_LANE0_QSGMII_LANE5 0x2
>>> +
>>> +#define SERDES4_LANE1_EDP_LANE1 0x0
>>> +#define SERDES4_LANE1_QSGMII_LANE6 0x2
>>> +
>>> +#define SERDES4_LANE2_EDP_LANE2 0x0
>>> +#define SERDES4_LANE2_QSGMII_LANE7 0x2
>>> +
>>> +#define SERDES4_LANE3_EDP_LANE3 0x0
>>> +#define SERDES4_LANE3_QSGMII_LANE8 0x2
>>> +
>>> +#endif /* _DT_BINDINGS_J721E_WIZ */
>>> --
>>> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
>>> Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
>>>
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v2 3/6] arm64: dts: ti: k3-j721e-main: Add serdes_ln_ctrl node to select SERDES lane mux
2020-03-19 11:37 ` Kishon Vijay Abraham I
2020-04-23 7:03 ` Roger Quadros
@ 2020-04-24 20:15 ` Rob Herring
1 sibling, 0 replies; 11+ messages in thread
From: Rob Herring @ 2020-04-24 20:15 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Roger Quadros, Tero Kristo, Nishanth Menon, Sekhar Nori,
Vignesh R, devicetree, linux-kernel@vger.kernel.org
On Thu, Mar 19, 2020 at 5:32 AM Kishon Vijay Abraham I <kishon@ti.com> wrote:
>
> Hi Rob,
>
> On 11/03/20 2:39 am, Rob Herring wrote:
> > On Tue, Mar 03, 2020 at 12:17:19PM +0200, Roger Quadros wrote:
> >> From: Kishon Vijay Abraham I <kishon@ti.com>
> >>
> >> Add serdes_ln_ctrl node used for selecting SERDES lane mux.
> >>
> >> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> >> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
> >> Signed-off-by: Roger Quadros <rogerq@ti.com>
> >> ---
> >> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 27 ++++++++++++
> >> include/dt-bindings/mux/mux-j721e-wiz.h | 53 +++++++++++++++++++++++
> >> 2 files changed, 80 insertions(+)
> >> create mode 100644 include/dt-bindings/mux/mux-j721e-wiz.h
> >>
> >> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> >> index cbaadee5bfdc..c5d54af37e91 100644
> >> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> >> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> >> @@ -5,6 +5,8 @@
> >> * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
> >> */
> >> #include <dt-bindings/phy/phy.h>
> >> +#include <dt-bindings/mux/mux.h>
> >> +#include <dt-bindings/mux/mux-j721e-wiz.h>
> >>
> >> &cbass_main {
> >> msmc_ram: sram@70000000 {
> >> @@ -19,6 +21,31 @@
> >> };
> >> };
> >>
> >> + scm_conf: scm-conf@100000 {
> >> + compatible = "syscon", "simple-mfd", "ti,j721e-system-controller";
> >
> > Wrong ordering. Most significant first.
> >
> >> + reg = <0 0x00100000 0 0x1c000>;
> >> + #address-cells = <1>;
> >> + #size-cells = <1>;
> >> + ranges = <0x0 0x0 0x00100000 0x1c000>;
> >> +
> >> + serdes_ln_ctrl: serdes-ln-ctrl@4080 {
> >
> > Your syscon.yaml change is not valid if you have child nodes. Do a
> > specific binding for this block.
>
> Do you mean in addition to having platform specific binding for
> scm-conf, I need to have platform specific binding for serdes-ln-ctrl.
I mean 'dt-bindings: syscon: Add TI's J721E specific compatible string'.
While not currently enforced because 'unevaluatedProperties: false'
doesn't yet do anything, the intent with syscon.yaml is child nodes
are not allowed. If you have child nodes, you need your own schema.
Rob
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 4/6] arm64: dts: ti: k3-j721e-main.dtsi: Add USB to SERDES MUX
2020-03-03 10:17 [PATCH v2 0/6] arm64: ti: k3-j721e: Add SERDES PHY and USB3.0 support Roger Quadros
` (2 preceding siblings ...)
2020-03-03 10:17 ` [PATCH v2 3/6] arm64: dts: ti: k3-j721e-main: Add serdes_ln_ctrl node to select SERDES lane mux Roger Quadros
@ 2020-03-03 10:17 ` Roger Quadros
2020-03-03 10:17 ` [PATCH v2 5/6] arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0 Roger Quadros
2020-03-03 10:17 ` [PATCH v2 6/6] arm64: dts: k3-j721e-proc-board: Add wait time for sampling Type-C DIR line Roger Quadros
5 siblings, 0 replies; 11+ messages in thread
From: Roger Quadros @ 2020-03-03 10:17 UTC (permalink / raw)
To: t-kristo
Cc: robh, kishon, nm, nsekhar, vigneshr, devicetree, linux-kernel,
Roger Quadros
The USB controllers can be connected to one of the 2 SERDESes
using a MUX. Add a MUX controller node fot that.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index c5d54af37e91..09b74f595f92 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -44,6 +44,13 @@
<MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
<SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
};
+
+ usb_serdes_mux: mux-controller@4000 {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
+ <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
+ };
};
gic500: interrupt-controller@1800000 {
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 5/6] arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0
2020-03-03 10:17 [PATCH v2 0/6] arm64: ti: k3-j721e: Add SERDES PHY and USB3.0 support Roger Quadros
` (3 preceding siblings ...)
2020-03-03 10:17 ` [PATCH v2 4/6] arm64: dts: ti: k3-j721e-main.dtsi: Add USB to SERDES MUX Roger Quadros
@ 2020-03-03 10:17 ` Roger Quadros
2020-03-03 10:17 ` [PATCH v2 6/6] arm64: dts: k3-j721e-proc-board: Add wait time for sampling Type-C DIR line Roger Quadros
5 siblings, 0 replies; 11+ messages in thread
From: Roger Quadros @ 2020-03-03 10:17 UTC (permalink / raw)
To: t-kristo
Cc: robh, kishon, nm, nsekhar, vigneshr, devicetree, linux-kernel,
Roger Quadros
USB0 supports super-speed mode on the EVM. Enable that.
On the EVM, USB0 uses SERDES3 for super-speed lane.
Since USB0 is a type-C port, it needs to support lane swapping
for cable flip support. This is provided using SERDES lane
swap feature. Provide the Type-C cable orientation GPIO
to the SERDES Wrapper driver.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
.../dts/ti/k3-j721e-common-proc-board.dts | 32 +++++++++++++++++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 7a5c3d4adadd..f057322b8c11 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -59,6 +59,7 @@
main_usbss0_pins_default: main_usbss0_pins_default {
pinctrl-single,pins = <
J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
+ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
>;
};
@@ -310,16 +311,43 @@
status = "disabled";
};
+&usb_serdes_mux {
+ idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
+};
+
+&serdes_ln_ctrl {
+ idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
+ <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
+ <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
+ <SERDES3_LANE0_USB3_0_SWAP>, <SERDES3_LANE1_USB3_0>,
+ <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
+};
+
+&serdes_wiz3 {
+ typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
+};
+
+&serdes3 {
+ serdes3_usb_link: link@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
+ };
+};
+
&usbss0 {
pinctrl-names = "default";
pinctrl-0 = <&main_usbss0_pins_default>;
- ti,usb2-only;
ti,vbus-divider;
};
&usb0 {
dr_mode = "otg";
- maximum-speed = "high-speed";
+ maximum-speed = "super-speed";
+ phys = <&serdes3_usb_link>;
+ phy-names = "cdns3,usb3-phy";
};
&usbss1 {
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 6/6] arm64: dts: k3-j721e-proc-board: Add wait time for sampling Type-C DIR line
2020-03-03 10:17 [PATCH v2 0/6] arm64: ti: k3-j721e: Add SERDES PHY and USB3.0 support Roger Quadros
` (4 preceding siblings ...)
2020-03-03 10:17 ` [PATCH v2 5/6] arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0 Roger Quadros
@ 2020-03-03 10:17 ` Roger Quadros
5 siblings, 0 replies; 11+ messages in thread
From: Roger Quadros @ 2020-03-03 10:17 UTC (permalink / raw)
To: t-kristo
Cc: robh, kishon, nm, nsekhar, vigneshr, devicetree, linux-kernel,
Roger Quadros
The Type-C compainon chip on the board needs ~133ms (tCCB_DEFAULT)
to debounce the CC lines in order to detect attach and plug orientation
and reflect the correct DIR status. [1]
On the EVM however we need to wait upto 700ms before sampling the
Type-C DIR line else we can get incorrect direction state.
[1] http://www.ti.com/lit/ds/symlink/tusb321.pdf
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index f057322b8c11..964a46e7af5e 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -325,6 +325,7 @@
&serdes_wiz3 {
typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
+ typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
};
&serdes3 {
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related [flat|nested] 11+ messages in thread