Re: [Intel-gfx] [PATCH v4 6/7] drm/i915/dp: Register definition for DP compliance register

From: Manasi Navare <manasi.d.navare@intel.com>
To: Animesh Manna <animesh.manna@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v4 6/7] drm/i915/dp: Register definition for DP compliance register
Date: Thu, 12 Mar 2020 16:08:43 -0700	[thread overview]
Message-ID: <20200312230843.GE8846@intel.com> (raw)
In-Reply-To: <20200310153745.22814-7-animesh.manna@intel.com>

Hi Animesh,

Here all the DP_COMP_CTL and DP_COMP_PAT register offsets should
be pipe based like we changed in the intel_dp_update_phy_pattern()
Since it could be on Port B but still use Pipe A and it should in that
case write to DDi_DP_COMP_CTL_A

On Tue, Mar 10, 2020 at 09:07:44PM +0530, Animesh Manna wrote:
> DP_COMP_CTL and DP_COMP_PAT register used to program DP
> compliance pattern.
> 
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 79ae9654dac9..7de4786b4882 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9786,6 +9786,26 @@ enum skl_power_gate {
>  #define  DDI_BUF_BALANCE_LEG_ENABLE	(1 << 31)
>  #define DDI_BUF_TRANS_HI(port, i)	_MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
>  
> +/* DDI DP Compliance Control */
> +#define DDI_DP_COMP_CTL_A                      0x605F0
> +#define DDI_DP_COMP_CTL_B                      0x615F0

You skipped defs for for _CTL_C and CTL_D (all 4 pipes on TGL)

> +#define DDI_DP_COMP_CTL(port) _MMIO_PORT(port, DDI_DP_COMP_CTL_A, \
> +					 DDI_DP_COMP_CTL_B)

Change this macro accordingly to select from 4 pipe addresses

> +#define  DDI_DP_COMP_CTL_ENABLE                        (1 << 31)
> +#define  DDI_DP_COMP_CTL_D10_2                 (0 << 28)
> +#define  DDI_DP_COMP_CTL_SCRAMBLED_0           (1 << 28)
> +#define  DDI_DP_COMP_CTL_PRBS7                 (2 << 28)
> +#define  DDI_DP_COMP_CTL_CUSTOM80                      (3 << 28)
> +#define  DDI_DP_COMP_CTL_HBR2                  (4 << 28)
> +#define  DDI_DP_COMP_CTL_SCRAMBLED_1           (5 << 28)
> +#define  DDI_DP_COMP_CTL_HBR2_RESET            (0xFC << 0)
> +
> +/* DDI DP Compliance Pattern */
> +#define DDI_DP_COMP_PAT_A                      0x605F4
> +#define DDI_DP_COMP_PAT_B                      0x615F4
> +#define DDI_DP_COMP_PAT(port, i) _MMIO(_PORT(port, DDI_DP_COMP_PAT_A, \
> +					     DDI_DP_COMP_PAT_B) + (i) * 4)

Same here to use pipe based offsets and define PAT_C and PAT_D as well

Manasi

> +
>  /* Sideband Interface (SBI) is programmed indirectly, via
>   * SBI_ADDR, which contains the register offset; and SBI_DATA,
>   * which contains the payload */
> -- 
> 2.24.0
> 
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