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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Manna, Animesh" <animesh.manna@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v6 6/7] drm/i915/dp: Register definition for DP compliance register
Date: Thu, 19 Mar 2020 18:02:22 +0200	[thread overview]
Message-ID: <20200319160222.GK13686@intel.com> (raw)
In-Reply-To: <ce9d15bf-d05b-305b-f94b-7ad6f5092306@intel.com>

On Thu, Mar 19, 2020 at 12:09:18PM +0530, Manna, Animesh wrote:
> On 19-03-2020 01:34, Manasi Navare wrote:
> > On Wed, Mar 18, 2020 at 12:05:14PM +0530, Animesh Manna wrote:
> >> DP_COMP_CTL and DP_COMP_PAT register used to program DP
> >> compliance pattern.
> >>
> >> v1: Initial patch.
> >> v2: used pipe instead of port in macro definition. [Manasi]
> >> v3: used trans_offset for offset calculation. [Manasi]
> >>
> >> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> >> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++++++++++
> >>   1 file changed, 16 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index 309cb7d96b35..8b6c9fbfe74b 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -9792,6 +9792,22 @@ enum skl_power_gate {
> >>   #define  DDI_BUF_BALANCE_LEG_ENABLE	(1 << 31)
> >>   #define DDI_BUF_TRANS_HI(port, i)	_MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
> >>   
> >> +/* DDI DP Compliance Control */
> >> +#define _DDI_DP_COMP_CTL_A			0x605F0
> >> +#define DDI_DP_COMP_CTL(pipe)			_MMIO_TRANS2(pipe, _DDI_DP_COMP_CTL_A)
> > Any reason why you couldnt use _MMIO_PIPE2 ?
> 
> As DP_COMP_CTL is part of transcoder register group, so I choose _MMIO_TRANS2 for calculation. Yes _MMIO_PIPE2 will also work as the offset difference between subsequent pipe is same (0x1000).

The preference is:
1. _MMIO_PIPE()/etc. for evenly spaced things
2. _MMIO_PIPE2()/etc. for regular but not evenly spaced stuff
3. _PICK() where the above two fail

There are probably a few places that do violate that though.
We should probably fix those to not give people the wrong ideas.

-- 
Ville Syrjälä
Intel
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  reply	other threads:[~2020-03-19 16:02 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-16 10:37 [Intel-gfx] [PATCH v5 0/7] DP Phy compliance auto test Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 1/7] drm/amd/display: Align macro name as per DP spec Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 2/7] drm/dp: get/set phy compliance pattern Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 3/7] drm/i915/dp: Made intel_dp_adjust_train() non-static Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 4/7] drm/i915/dp: Preparation for DP phy compliance auto test Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 5/7] drm/i915/dp: Add debugfs entry for DP phy compliance Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 6/7] drm/i915/dp: Register definition for DP compliance register Animesh Manna
2020-03-17  0:13   ` Manasi Navare
2020-03-18  6:35     ` [Intel-gfx] [PATCH v6 " Animesh Manna
2020-03-18 20:04       ` Manasi Navare
2020-03-19  6:39         ` Manna, Animesh
2020-03-19 16:02           ` Ville Syrjälä [this message]
2020-03-19 21:51             ` Manasi Navare
2020-03-24  5:11               ` [Intel-gfx] [PATCH v7 " Animesh Manna
2020-03-27 18:45                 ` Manasi Navare
2020-03-30  4:01                   ` Manna, Animesh
2020-03-31  0:22                     ` Manasi Navare
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 7/7] drm/i915/dp: Program vswing, pre-emphasis, test-pattern Animesh Manna
2020-04-06 15:09   ` Manasi Navare
2020-03-16 19:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success for DP Phy compliance auto test (rev7) Patchwork
2020-03-17  3:48 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-03-18  8:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success for DP Phy compliance auto test (rev8) Patchwork
2020-03-18 10:47 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-03-24  5:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DP Phy compliance auto test (rev9) Patchwork
2020-03-24  6:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-03-24  7:47 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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