All of lore.kernel.org
 help / color / mirror / Atom feed
From: Manasi Navare <manasi.d.navare@intel.com>
To: Animesh Manna <animesh.manna@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v5 7/7] drm/i915/dp: Program vswing, pre-emphasis, test-pattern
Date: Mon, 6 Apr 2020 08:09:38 -0700	[thread overview]
Message-ID: <20200406150938.GA433@intel.com> (raw)
In-Reply-To: <20200316103759.12867-8-animesh.manna@intel.com>

On Mon, Mar 16, 2020 at 04:07:59PM +0530, Animesh Manna wrote:
> This patch process phy compliance request by programming requested
> vswing, pre-emphasis and test pattern.
> 
> v1: Initial patch.
> v2: Fixes added during testing with test-scope. (Khaled/Clint/Manasi)
> - pipe used as argument during registers programming instead of port.
> - TRANS_CONF must be disable/enable as well during ddi disable/enable.
> - harcoded PLTPAT 80 bit custom pattern as the DPR-100 does not set it
> in the sink’s DPCDs
> - TRANS_DDI_FUNC_CTL DDI_Select (Bits 27:30) need to reset/set during
> disable/enable.
> v3: used macros instead of numbers and some cosmetic changes. [Manasi]
> 
> Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com>

Looks good to me,

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 147 ++++++++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dp.h |   1 +
>  2 files changed, 148 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 16a4a48c8168..8846471a49b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5020,6 +5020,151 @@ static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
>  	return DP_TEST_ACK;
>  }
>  
> +static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
> +{
> +	struct drm_i915_private *dev_priv =
> +			to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
> +	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_dp_phy_test_params *data =
> +			&intel_dp->compliance.test_data.phytest;
> +	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
> +	enum pipe pipe = crtc->pipe;
> +	u32 pattern_val;
> +
> +	switch (data->phy_pattern) {
> +	case DP_PHY_TEST_PATTERN_NONE:
> +		DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
> +		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
> +		break;
> +	case DP_PHY_TEST_PATTERN_D10_2:
> +		DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
> +		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
> +			       DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
> +		break;
> +	case DP_PHY_TEST_PATTERN_ERROR_COUNT:
> +		DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
> +		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
> +			       DDI_DP_COMP_CTL_ENABLE |
> +			       DDI_DP_COMP_CTL_SCRAMBLED_0);
> +		break;
> +	case DP_PHY_TEST_PATTERN_PRBS7:
> +		DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
> +		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
> +			       DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
> +		break;
> +	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
> +		/*
> +		 * FIXME: Ideally pattern should come from DPCD 0x250. As
> +		 * current firmware of DPR-100 could not set it, so hardcoding
> +		 * now for complaince test.
> +		 */
> +		DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
> +		pattern_val = 0x3e0f83e0;
> +		intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
> +		pattern_val = 0x0f83e0f8;
> +		intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
> +		pattern_val = 0x0000f83e;
> +		intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
> +		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
> +			       DDI_DP_COMP_CTL_ENABLE |
> +			       DDI_DP_COMP_CTL_CUSTOM80);
> +		break;
> +	case DP_PHY_TEST_PATTERN_CP2520:
> +		/*
> +		 * FIXME: Ideally pattern should come from DPCD 0x24A. As
> +		 * current firmware of DPR-100 could not set it, so hardcoding
> +		 * now for complaince test.
> +		 */
> +		DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
> +		pattern_val = 0xFB;
> +		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
> +			       DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
> +			       pattern_val);
> +		break;
> +	default:
> +		WARN(1, "Invalid Phy Test Pattern\n");
> +	}
> +}
> +
> +static void
> +intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
> +{
> +	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_device *dev = intel_dig_port->base.base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
> +	enum pipe pipe = crtc->pipe;
> +	u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
> +
> +	trans_ddi_func_ctl_value = intel_de_read(dev_priv,
> +						 TRANS_DDI_FUNC_CTL(pipe));
> +	trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
> +	dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
> +
> +	trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
> +				      TGL_TRANS_DDI_PORT_MASK);
> +	trans_conf_value &= ~PIPECONF_ENABLE;
> +	dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
> +
> +	intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
> +	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
> +		       trans_ddi_func_ctl_value);
> +	intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
> +}
> +
> +static void
> +intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
> +{
> +	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_device *dev = intel_dig_port->base.base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	enum port port = intel_dig_port->base.port;
> +	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
> +	enum pipe pipe = crtc->pipe;
> +	u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
> +
> +	trans_ddi_func_ctl_value = intel_de_read(dev_priv,
> +						 TRANS_DDI_FUNC_CTL(pipe));
> +	trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
> +	dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
> +
> +	trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
> +				    TGL_TRANS_DDI_SELECT_PORT(port);
> +	trans_conf_value |= PIPECONF_ENABLE;
> +	dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
> +
> +	intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
> +	intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
> +	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
> +		       trans_ddi_func_ctl_value);
> +}
> +
> +void intel_dp_process_phy_request(struct intel_dp *intel_dp)
> +{
> +	struct drm_dp_phy_test_params *data =
> +		&intel_dp->compliance.test_data.phytest;
> +	u8 link_status[DP_LINK_STATUS_SIZE];
> +
> +	if (!intel_dp_get_link_status(intel_dp, link_status)) {
> +		DRM_DEBUG_KMS("failed to get link status\n");
> +		return;
> +	}
> +
> +	/* retrieve vswing & pre-emphasis setting */
> +	intel_dp_get_adjust_train(intel_dp, link_status);
> +
> +	intel_dp_autotest_phy_ddi_disable(intel_dp);
> +
> +	intel_dp_set_signal_levels(intel_dp);
> +
> +	intel_dp_phy_pattern_update(intel_dp);
> +
> +	intel_dp_autotest_phy_ddi_enable(intel_dp, data->num_lanes);
> +
> +	drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
> +				    link_status[DP_DPCD_REV]);
> +}
> +
>  static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
>  {
>  	u8 test_result = DP_TEST_NAK;
> @@ -5028,6 +5173,8 @@ static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
>  	if (test_result != DP_TEST_ACK)
>  		DRM_ERROR("Phy test preparation failed\n");
>  
> +	intel_dp_process_phy_request(intel_dp);
> +
>  	return test_result;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 0c7be8ed1423..0d22a230b32d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -115,6 +115,7 @@ void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
>  				  const struct intel_crtc_state *crtc_state,
>  				  const struct drm_connector_state *conn_state);
>  bool intel_digital_port_connected(struct intel_encoder *encoder);
> +void intel_dp_process_phy_request(struct intel_dp *intel_dp);
>  
>  static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
>  {
> -- 
> 2.24.0
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2020-04-06 15:07 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-16 10:37 [Intel-gfx] [PATCH v5 0/7] DP Phy compliance auto test Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 1/7] drm/amd/display: Align macro name as per DP spec Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 2/7] drm/dp: get/set phy compliance pattern Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 3/7] drm/i915/dp: Made intel_dp_adjust_train() non-static Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 4/7] drm/i915/dp: Preparation for DP phy compliance auto test Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 5/7] drm/i915/dp: Add debugfs entry for DP phy compliance Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 6/7] drm/i915/dp: Register definition for DP compliance register Animesh Manna
2020-03-17  0:13   ` Manasi Navare
2020-03-18  6:35     ` [Intel-gfx] [PATCH v6 " Animesh Manna
2020-03-18 20:04       ` Manasi Navare
2020-03-19  6:39         ` Manna, Animesh
2020-03-19 16:02           ` Ville Syrjälä
2020-03-19 21:51             ` Manasi Navare
2020-03-24  5:11               ` [Intel-gfx] [PATCH v7 " Animesh Manna
2020-03-27 18:45                 ` Manasi Navare
2020-03-30  4:01                   ` Manna, Animesh
2020-03-31  0:22                     ` Manasi Navare
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 7/7] drm/i915/dp: Program vswing, pre-emphasis, test-pattern Animesh Manna
2020-04-06 15:09   ` Manasi Navare [this message]
2020-03-16 19:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success for DP Phy compliance auto test (rev7) Patchwork
2020-03-17  3:48 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-03-18  8:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success for DP Phy compliance auto test (rev8) Patchwork
2020-03-18 10:47 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-03-24  5:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DP Phy compliance auto test (rev9) Patchwork
2020-03-24  6:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-03-24  7:47 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200406150938.GA433@intel.com \
    --to=manasi.d.navare@intel.com \
    --cc=animesh.manna@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.