diff for duplicates of <20200330232842.GA25358@bogus> diff --git a/a/1.txt b/N1/1.txt index b5d0e2b..4fcb449 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,11 +1,11 @@ On Fri, Mar 20, 2020 at 02:34:46PM +0100, Thierry Reding wrote: -> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +> From: Thierry Reding <treding@nvidia.com> > > The NVIDIA Tegra186 SoC contains an IP block that provides a register > interface for ten timers with a 29-bit counter that can generate one- > shot, periodic or watchdog interrupts. > -> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +> Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > .../bindings/timer/nvidia,tegra186-timer.yaml | 55 +++++++++++++++++++ > 1 file changed, 55 insertions(+) @@ -26,8 +26,8 @@ On Fri, Mar 20, 2020 at 02:34:46PM +0100, Thierry Reding wrote: > +title: NVIDIA Tegra186 timers > + > +maintainers: -> + - Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> -> + - Jonathan Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +> + - Thierry Reding <thierry.reding@gmail.com> +> + - Jonathan Hunter <jonathanh@nvidia.com> > + > +description: | > + The Tegra186 timer provides ten 29-bit timer counters and one 32-bit TSC diff --git a/a/content_digest b/N1/content_digest index a90153e..f379812 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,25 +1,24 @@ "ref\020200320133452.3705040-1-thierry.reding@gmail.com\0" "ref\020200320133452.3705040-2-thierry.reding@gmail.com\0" - "ref\020200320133452.3705040-2-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" - "From\0Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>\0" + "From\0Rob Herring <robh@kernel.org>\0" "Subject\0Re: [PATCH 1/7] dt-bindings: timer: Add bindings for NVIDIA Tegra186 timers\0" "Date\0Mon, 30 Mar 2020 17:28:42 -0600\0" - "To\0Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" - "Cc\0Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>" - Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> - linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - " linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" + "To\0Thierry Reding <thierry.reding@gmail.com>\0" + "Cc\0Thomas Gleixner <tglx@linutronix.de>" + Jon Hunter <jonathanh@nvidia.com> + linux-tegra@vger.kernel.org + devicetree@vger.kernel.org + " linux-kernel@vger.kernel.org\0" "\00:1\0" "b\0" "On Fri, Mar 20, 2020 at 02:34:46PM +0100, Thierry Reding wrote:\n" - "> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "> From: Thierry Reding <treding@nvidia.com>\n" "> \n" "> The NVIDIA Tegra186 SoC contains an IP block that provides a register\n" "> interface for ten timers with a 29-bit counter that can generate one-\n" "> shot, periodic or watchdog interrupts.\n" "> \n" - "> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "> Signed-off-by: Thierry Reding <treding@nvidia.com>\n" "> ---\n" "> .../bindings/timer/nvidia,tegra186-timer.yaml | 55 +++++++++++++++++++\n" "> 1 file changed, 55 insertions(+)\n" @@ -40,8 +39,8 @@ "> +title: NVIDIA Tegra186 timers\n" "> +\n" "> +maintainers:\n" - "> + - Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n" - "> + - Jonathan Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "> + - Thierry Reding <thierry.reding@gmail.com>\n" + "> + - Jonathan Hunter <jonathanh@nvidia.com>\n" "> +\n" "> +description: |\n" "> + The Tegra186 timer provides ten 29-bit timer counters and one 32-bit TSC\n" @@ -100,4 +99,4 @@ "> 2.24.1\n" > -3ffc4a8f0d77383d3a9fddd120ec289054479a7c0ad7ec727ce8ceb5121cc843 +5bf51e5e12ac19c1d09c6a6d31e8176c70182f0be0c8711156e05593ab4f77e2
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