From: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
To: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>,
Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH 1/7] dt-bindings: timer: Add bindings for NVIDIA Tegra186 timers
Date: Mon, 30 Mar 2020 17:28:42 -0600 [thread overview]
Message-ID: <20200330232842.GA25358@bogus> (raw)
In-Reply-To: <20200320133452.3705040-2-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Fri, Mar 20, 2020 at 02:34:46PM +0100, Thierry Reding wrote:
> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> The NVIDIA Tegra186 SoC contains an IP block that provides a register
> interface for ten timers with a 29-bit counter that can generate one-
> shot, periodic or watchdog interrupts.
>
> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> .../bindings/timer/nvidia,tegra186-timer.yaml | 55 +++++++++++++++++++
> 1 file changed, 55 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
>
> diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
> new file mode 100644
> index 000000000000..f9b55041a5ca
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
> @@ -0,0 +1,55 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra186 timers
> +
> +maintainers:
> + - Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> + - Jonathan Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> +
> +description: |
> + The Tegra186 timer provides ten 29-bit timer counters and one 32-bit TSC
> + (timestamp counter). The timers run at either a fixed 1 MHz clock rate
> + derived from the oscillator clock. Each timer can be programmed to raise
> + one-shot, periodic, or watchdog interrupts.
> +
> +properties:
> + compatible:
> + oneOf:
> + - description: NVIDIA Tegra186
> + items:
> + - const: nvidia,tegra186-timer
> +
> + - description: NVIDIA Tegra194
> + items:
> + - const: nvidia,tegra194-timer
> + - const: nvidia,tegra186-timer
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 10
required props?
Also, add:
additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + timer@3010000 {
> + compatible = "nvidia,tegra186-timer";
> + reg = <0x03010000 0x000e0000>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
Don't show status in examples.
> + };
> --
> 2.24.1
>
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Jon Hunter <jonathanh@nvidia.com>,
linux-tegra@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/7] dt-bindings: timer: Add bindings for NVIDIA Tegra186 timers
Date: Mon, 30 Mar 2020 17:28:42 -0600 [thread overview]
Message-ID: <20200330232842.GA25358@bogus> (raw)
In-Reply-To: <20200320133452.3705040-2-thierry.reding@gmail.com>
On Fri, Mar 20, 2020 at 02:34:46PM +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> The NVIDIA Tegra186 SoC contains an IP block that provides a register
> interface for ten timers with a 29-bit counter that can generate one-
> shot, periodic or watchdog interrupts.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> .../bindings/timer/nvidia,tegra186-timer.yaml | 55 +++++++++++++++++++
> 1 file changed, 55 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
>
> diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
> new file mode 100644
> index 000000000000..f9b55041a5ca
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
> @@ -0,0 +1,55 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra186 timers
> +
> +maintainers:
> + - Thierry Reding <thierry.reding@gmail.com>
> + - Jonathan Hunter <jonathanh@nvidia.com>
> +
> +description: |
> + The Tegra186 timer provides ten 29-bit timer counters and one 32-bit TSC
> + (timestamp counter). The timers run at either a fixed 1 MHz clock rate
> + derived from the oscillator clock. Each timer can be programmed to raise
> + one-shot, periodic, or watchdog interrupts.
> +
> +properties:
> + compatible:
> + oneOf:
> + - description: NVIDIA Tegra186
> + items:
> + - const: nvidia,tegra186-timer
> +
> + - description: NVIDIA Tegra194
> + items:
> + - const: nvidia,tegra194-timer
> + - const: nvidia,tegra186-timer
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 10
required props?
Also, add:
additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + timer@3010000 {
> + compatible = "nvidia,tegra186-timer";
> + reg = <0x03010000 0x000e0000>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
Don't show status in examples.
> + };
> --
> 2.24.1
>
next prev parent reply other threads:[~2020-03-30 23:28 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-20 13:34 [PATCH 0/7] clocksource: Add NVIDIA Tegra186 timers support Thierry Reding
2020-03-20 13:34 ` Thierry Reding
2020-03-20 13:34 ` [PATCH 5/7] arm64: tegra: Enable native timers on Jetson TX2 Thierry Reding
[not found] ` <20200320133452.3705040-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-03-20 13:34 ` [PATCH 1/7] dt-bindings: timer: Add bindings for NVIDIA Tegra186 timers Thierry Reding
2020-03-20 13:34 ` Thierry Reding
[not found] ` <20200320133452.3705040-2-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-03-30 23:28 ` Rob Herring [this message]
2020-03-30 23:28 ` Rob Herring
2020-03-20 13:34 ` [PATCH 2/7] clocksource: Add Tegra186 timers support Thierry Reding
2020-03-20 13:34 ` Thierry Reding
[not found] ` <20200320133452.3705040-3-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-03-20 14:39 ` Dmitry Osipenko
2020-03-20 14:39 ` Dmitry Osipenko
2020-03-20 15:04 ` Thierry Reding
2020-03-20 15:23 ` Dmitry Osipenko
2020-03-20 15:23 ` Dmitry Osipenko
2020-03-23 13:38 ` Thierry Reding
[not found] ` <5a559950-0497-b24f-6484-c2513375fe62-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-03-31 20:04 ` Thierry Reding
2020-03-31 20:04 ` Thierry Reding
2020-03-20 15:11 ` Dmitry Osipenko
2020-03-20 15:11 ` Dmitry Osipenko
[not found] ` <48b2099c-dd83-d4dc-aab4-8c6f68a215cf-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-03-20 15:38 ` Dmitry Osipenko
2020-03-20 15:38 ` Dmitry Osipenko
[not found] ` <da2a0501-664a-c5d0-7b13-174e5347eaf7-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-03-23 13:42 ` Thierry Reding
2020-03-23 13:42 ` Thierry Reding
2020-03-23 13:45 ` Dmitry Osipenko
2020-03-23 16:10 ` Dmitry Osipenko
[not found] ` <b3859b98-02a3-d197-735c-2c9a9fbe597c-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-03-31 19:58 ` Thierry Reding
2020-03-31 19:58 ` Thierry Reding
2020-03-20 13:34 ` [PATCH 3/7] arm64: tegra: Order nodes by unit-address on Tegra194 Thierry Reding
2020-03-20 13:34 ` Thierry Reding
2020-03-20 13:34 ` [PATCH 4/7] arm64: tegra: Add native timer support on Tegra186 Thierry Reding
2020-03-20 13:34 ` Thierry Reding
2020-03-20 13:34 ` [PATCH 6/7] arm64: tegra: Add native timer support on Tegra194 Thierry Reding
2020-03-20 13:34 ` Thierry Reding
2020-03-20 13:34 ` [PATCH 7/7] arm64: tegra: Enable native timers on Jetson AGX Xavier Thierry Reding
2020-03-20 13:34 ` Thierry Reding
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