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* [Intel-gfx] [PATCH v2 1/3] drm/i915/dp: Return the right vswing tables
@ 2020-03-30 21:00 José Roberto de Souza
  2020-03-30 21:00 ` [Intel-gfx] [PATCH v2 2/3] drm/i915/dp/ehl: Update vswing table for HBR and RBR José Roberto de Souza
                   ` (4 more replies)
  0 siblings, 5 replies; 9+ messages in thread
From: José Roberto de Souza @ 2020-03-30 21:00 UTC (permalink / raw)
  To: intel-gfx

DDI ports have its encoders initialized with INTEL_OUTPUT_DDI type and
later eDP ports that have the type changed to INTEL_OUTPUT_EDP.
But for all other DDI ports it can drive HDMI or DP depending on what
user connects to the ports.

ehl_get_combo_buf_trans() and tgl_get_combo_buf_trans() was checking
for INTEL_OUTPUT_DP that was never true, causing wrong vswing tables
being used.

So here replacing the INTEL_OUTPUT_DP checks by the valid output types
that this functions receives as parameters. HDMI cases will be
correctly handled as it do not use encoder->type, instead it calls the
functions with INTEL_OUTPUT_HDMI as type parameter and HDMI don't have
retraining.

v2:
changed INTEL_OUTPUT_DDI to INTEL_OUTPUT_EDP and INTEL_OUTPUT_HDMI

Fixes: bd3cf6f7ce20 ("drm/i915/dp/tgl+: Update combo phy vswing tables")
Cc: Clinton A Taylor <clinton.a.taylor@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 916a802af788..053b21c11b0c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -947,7 +947,8 @@ static const struct cnl_ddi_buf_trans *
 ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
 			int *n_entries)
 {
-	if (type == INTEL_OUTPUT_DP && rate > 270000) {
+	if (type != INTEL_OUTPUT_HDMI && type != INTEL_OUTPUT_EDP &&
+	    rate > 270000) {
 		*n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_hbr2_hbr3);
 		return ehl_combo_phy_ddi_translations_hbr2_hbr3;
 	}
@@ -959,7 +960,7 @@ static const struct cnl_ddi_buf_trans *
 tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
 			int *n_entries)
 {
-	if (type != INTEL_OUTPUT_DP) {
+	if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) {
 		return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries);
 	} else if (rate > 270000) {
 		*n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
-- 
2.26.0

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^ permalink raw reply related	[flat|nested] 9+ messages in thread
end of thread, other threads:[~2020-03-31 23:52 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-03-30 21:00 [Intel-gfx] [PATCH v2 1/3] drm/i915/dp: Return the right vswing tables José Roberto de Souza
2020-03-30 21:00 ` [Intel-gfx] [PATCH v2 2/3] drm/i915/dp/ehl: Update vswing table for HBR and RBR José Roberto de Souza
2020-03-31 15:37   ` Ville Syrjälä
2020-03-30 21:00 ` [Intel-gfx] [PATCH v2 3/3] drm/i915/tc/icl: Update TC vswing tables José Roberto de Souza
2020-03-31 20:20   ` Taylor, Clinton A
2020-03-31  1:39 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/3] drm/i915/dp: Return the right " Patchwork
2020-03-31 10:41 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-03-31 20:48   ` Souza, Jose
2020-03-31 23:52 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [v2,1/3] drm/i915/dp: Return the right vswing tables (rev2) Patchwork

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