From: kbuild test robot <lkp@intel.com>
To: kbuild-all@lists.01.org
Subject: Re: [v7 PATCH 6/6] PCI: hip: Add handling of HiSilicon HIP PCIe controller errors
Date: Wed, 08 Apr 2020 06:03:28 +0800 [thread overview]
Message-ID: <202004080511.2gesDFeV%lkp@intel.com> (raw)
In-Reply-To: <20200407120045.958-7-shiju.jose@huawei.com>
[-- Attachment #1: Type: text/plain, Size: 4121 bytes --]
Hi Shiju,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on v5.6]
[also build test WARNING on next-20200407]
[cannot apply to pm/linux-next pci/next linus/master linux/master]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Shiju-Jose/ACPI-APEI-Add-support-to-notify-non-fatal-HW-errors/20200408-014447
base: 7111951b8d4973bda27ff663f2cf18b663d15b48
config: i386-allyesconfig (attached as .config)
compiler: gcc-7 (Ubuntu 7.5.0-6ubuntu2) 7.5.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
drivers/pci/controller/pcie-hisi-error.c: In function 'hisi_pcie_handle_error':
>> drivers/pci/controller/pcie-hisi-error.c:246:1: warning: the frame size of 1124 bytes is larger than 1024 bytes [-Wframe-larger-than=]
}
^
vim +246 drivers/pci/controller/pcie-hisi-error.c
181
182 static void hisi_pcie_handle_error(const struct hisi_pcie_error_data *error,
183 struct platform_device *pdev)
184 {
185 char buf[HISI_PCIE_ERR_INFO_SIZE];
186 char *p = buf, *end = buf + sizeof(buf);
187 struct device *dev = &pdev->dev;
188 u32 i;
189 int rc;
190
191 if (error->val_bits == 0) {
192 dev_warn(dev, "%s: no valid error information\n", __func__);
193 return;
194 }
195
196 /* Logging */
197 p += snprintf(p, end - p, "[ Table version=%d ", error->version);
198 if (error->val_bits & HISI_PCIE_LOCAL_VALID_SOC_ID)
199 p += snprintf(p, end - p, "SOC ID=%d ", error->soc_id);
200
201 if (error->val_bits & HISI_PCIE_LOCAL_VALID_SOCKET_ID)
202 p += snprintf(p, end - p, "socket ID=%d ", error->socket_id);
203
204 if (error->val_bits & HISI_PCIE_LOCAL_VALID_NIMBUS_ID)
205 p += snprintf(p, end - p, "nimbus ID=%d ", error->nimbus_id);
206
207 if (error->val_bits & HISI_PCIE_LOCAL_VALID_SUB_MODULE_ID)
208 p += snprintf(p, end - p, "sub module=%s ",
209 hisi_pcie_sub_module_name(error->sub_module_id));
210
211 if (error->val_bits & HISI_PCIE_LOCAL_VALID_CORE_ID)
212 p += snprintf(p, end - p, "core ID=core%d ", error->core_id);
213
214 if (error->val_bits & HISI_PCIE_LOCAL_VALID_PORT_ID)
215 p += snprintf(p, end - p, "port ID=port%d ", error->port_id);
216
217 if (error->val_bits & HISI_PCIE_LOCAL_VALID_ERR_SEVERITY)
218 p += snprintf(p, end - p, "error severity=%s ",
219 hisi_pcie_error_severity(error->err_severity));
220
221 if (error->val_bits & HISI_PCIE_LOCAL_VALID_ERR_TYPE)
222 p += snprintf(p, end - p, "error type=0x%x ", error->err_type);
223
224 p += snprintf(p, end - p, "]\n");
225 dev_info(dev, "\nHISI : HIP : PCIe controller error\n");
226 dev_info(dev, "%s\n", buf);
227
228 dev_info(dev, "Reg Dump:\n");
229 for (i = 0; i < HISI_PCIE_ERR_MISC_REGS; i++) {
230 if (error->val_bits &
231 BIT_ULL(HISI_PCIE_LOCAL_VALID_ERR_MISC + i))
232 dev_info(dev,
233 "ERR_MISC_%d=0x%x\n", i, error->err_misc[i]);
234 }
235
236 /* Recovery for the PCIe controller errors */
237 if (error->err_severity == HISI_ERR_SEV_RECOVERABLE) {
238 /* try reset PCI port for the error recovery */
239 rc = hisi_pcie_port_do_recovery(pdev, error->socket_id,
240 HISI_PCIE_PORT_ID(error->core_id, error->port_id));
241 if (rc) {
242 dev_info(dev, "fail to do hisi pcie port reset\n");
243 return;
244 }
245 }
> 246 }
247
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 71594 bytes --]
WARNING: multiple messages have this Message-ID (diff)
From: kbuild test robot <lkp@intel.com>
To: Shiju Jose <shiju.jose@huawei.com>
Cc: kbuild-all@lists.01.org, linux-acpi@vger.kernel.org,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
rjw@rjwysocki.net, bp@alien8.de, james.morse@arm.com,
helgaas@kernel.org, lenb@kernel.org, tony.luck@intel.com,
dan.carpenter@oracle.com, gregkh@linuxfoundation.org,
zhangliguang@linux.alibaba.com, tglx@linutronix.de
Subject: Re: [v7 PATCH 6/6] PCI: hip: Add handling of HiSilicon HIP PCIe controller errors
Date: Wed, 8 Apr 2020 06:03:28 +0800 [thread overview]
Message-ID: <202004080511.2gesDFeV%lkp@intel.com> (raw)
In-Reply-To: <20200407120045.958-7-shiju.jose@huawei.com>
[-- Attachment #1: Type: text/plain, Size: 4017 bytes --]
Hi Shiju,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on v5.6]
[also build test WARNING on next-20200407]
[cannot apply to pm/linux-next pci/next linus/master linux/master]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Shiju-Jose/ACPI-APEI-Add-support-to-notify-non-fatal-HW-errors/20200408-014447
base: 7111951b8d4973bda27ff663f2cf18b663d15b48
config: i386-allyesconfig (attached as .config)
compiler: gcc-7 (Ubuntu 7.5.0-6ubuntu2) 7.5.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
drivers/pci/controller/pcie-hisi-error.c: In function 'hisi_pcie_handle_error':
>> drivers/pci/controller/pcie-hisi-error.c:246:1: warning: the frame size of 1124 bytes is larger than 1024 bytes [-Wframe-larger-than=]
}
^
vim +246 drivers/pci/controller/pcie-hisi-error.c
181
182 static void hisi_pcie_handle_error(const struct hisi_pcie_error_data *error,
183 struct platform_device *pdev)
184 {
185 char buf[HISI_PCIE_ERR_INFO_SIZE];
186 char *p = buf, *end = buf + sizeof(buf);
187 struct device *dev = &pdev->dev;
188 u32 i;
189 int rc;
190
191 if (error->val_bits == 0) {
192 dev_warn(dev, "%s: no valid error information\n", __func__);
193 return;
194 }
195
196 /* Logging */
197 p += snprintf(p, end - p, "[ Table version=%d ", error->version);
198 if (error->val_bits & HISI_PCIE_LOCAL_VALID_SOC_ID)
199 p += snprintf(p, end - p, "SOC ID=%d ", error->soc_id);
200
201 if (error->val_bits & HISI_PCIE_LOCAL_VALID_SOCKET_ID)
202 p += snprintf(p, end - p, "socket ID=%d ", error->socket_id);
203
204 if (error->val_bits & HISI_PCIE_LOCAL_VALID_NIMBUS_ID)
205 p += snprintf(p, end - p, "nimbus ID=%d ", error->nimbus_id);
206
207 if (error->val_bits & HISI_PCIE_LOCAL_VALID_SUB_MODULE_ID)
208 p += snprintf(p, end - p, "sub module=%s ",
209 hisi_pcie_sub_module_name(error->sub_module_id));
210
211 if (error->val_bits & HISI_PCIE_LOCAL_VALID_CORE_ID)
212 p += snprintf(p, end - p, "core ID=core%d ", error->core_id);
213
214 if (error->val_bits & HISI_PCIE_LOCAL_VALID_PORT_ID)
215 p += snprintf(p, end - p, "port ID=port%d ", error->port_id);
216
217 if (error->val_bits & HISI_PCIE_LOCAL_VALID_ERR_SEVERITY)
218 p += snprintf(p, end - p, "error severity=%s ",
219 hisi_pcie_error_severity(error->err_severity));
220
221 if (error->val_bits & HISI_PCIE_LOCAL_VALID_ERR_TYPE)
222 p += snprintf(p, end - p, "error type=0x%x ", error->err_type);
223
224 p += snprintf(p, end - p, "]\n");
225 dev_info(dev, "\nHISI : HIP : PCIe controller error\n");
226 dev_info(dev, "%s\n", buf);
227
228 dev_info(dev, "Reg Dump:\n");
229 for (i = 0; i < HISI_PCIE_ERR_MISC_REGS; i++) {
230 if (error->val_bits &
231 BIT_ULL(HISI_PCIE_LOCAL_VALID_ERR_MISC + i))
232 dev_info(dev,
233 "ERR_MISC_%d=0x%x\n", i, error->err_misc[i]);
234 }
235
236 /* Recovery for the PCIe controller errors */
237 if (error->err_severity == HISI_ERR_SEV_RECOVERABLE) {
238 /* try reset PCI port for the error recovery */
239 rc = hisi_pcie_port_do_recovery(pdev, error->socket_id,
240 HISI_PCIE_PORT_ID(error->core_id, error->port_id));
241 if (rc) {
242 dev_info(dev, "fail to do hisi pcie port reset\n");
243 return;
244 }
245 }
> 246 }
247
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 71594 bytes --]
next prev parent reply other threads:[~2020-04-07 22:03 UTC|newest]
Thread overview: 101+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <Shiju Jose>
2019-06-17 14:28 ` [PATCH 0/6] rasdaemon:add logging of HiSilicon HIP08 non-standard H/W errors and changes in the error decoding code Shiju Jose
2019-06-17 14:28 ` [PATCH 1/6] rasdaemon:print non-standard error data if not decoded Shiju Jose
2019-06-17 14:28 ` [PATCH 2/6] rasdaemon: rearrange HiSilicon HIP07 decoding function table Shiju Jose
2019-06-17 14:28 ` [PATCH 3/6] rasdaemon: update iteration logic for the non-standard error decoding functions Shiju Jose
2019-06-17 14:28 ` [PATCH 4/6] rasdaemon:add logging HiSilicon HIP08 H/W errors reported in the OEM format1 Shiju Jose
2019-06-17 14:28 ` [PATCH 5/6] rasdaemon:add logging HiSilicon HIP08 H/W errors reported in the OEM format2 Shiju Jose
2019-06-17 14:28 ` [PATCH 6/6] rasdaemon:add logging HiSilicon HIP08 PCIe local errors Shiju Jose
2019-06-21 18:42 ` [PATCH 0/6] rasdaemon:add logging of HiSilicon HIP08 non-standard H/W errors and changes in the error decoding code Mauro Carvalho Chehab
2019-08-12 10:11 ` [PATCH RFC 0/4] ACPI: APEI: Add support to notify the vendor specific HW errors Shiju Jose
2019-08-12 10:11 ` [PATCH RFC 1/4] " Shiju Jose
2019-08-21 17:23 ` James Morse
2019-08-22 16:57 ` Shiju Jose
2019-08-12 10:11 ` [PATCH RFC 2/4] ACPI: APEI: Add ghes_handle_memory_failure to the new notification method Shiju Jose
2019-08-21 17:22 ` James Morse
2019-08-22 16:57 ` Shiju Jose
2019-08-12 10:11 ` [PATCH RFC 3/4] ACPI: APEI: Add ghes_handle_aer " Shiju Jose
2019-08-12 10:11 ` [PATCH RFC 4/4] ACPI: APEI: Add log_arm_hw_error " Shiju Jose
2019-08-21 17:22 ` [PATCH RFC 0/4] ACPI: APEI: Add support to notify the vendor specific HW errors James Morse
2019-08-22 16:56 ` Shiju Jose
2019-10-03 17:21 ` James Morse
2019-10-16 16:33 ` [PATCH 0/7] rasdaemon: add fixes, database closure and signal handling Shiju Jose
2019-10-16 16:33 ` [PATCH 1/7] rasdaemon: fix cleanup issues in ras-events.c:read_ras_event_all_cpus() Shiju Jose
2019-10-16 16:33 ` [PATCH 2/7] rasdaemon: fix memory leak in ras-events.c:handle_ras_events() Shiju Jose
2019-10-16 16:33 ` [PATCH 3/7] rasdaemon: fix missing fclose in ras-events.c:select_tracing_timestamp() Shiju Jose
2019-10-16 16:33 ` [PATCH 4/7] rasdaemon: fix memory leak in ras-events.c:add_event_handler() Shiju Jose
2019-10-16 16:33 ` [PATCH 5/7] rasdaemon: delete multiple definitions of ARRAY_SIZE Shiju Jose
2019-10-16 16:34 ` [PATCH 6/7] rasdaemon: add closure and cleanups for the database Shiju Jose
2019-10-16 16:34 ` [PATCH 7/7] rasdaemon: add signal handling for the cleanup Shiju Jose
2019-11-13 16:38 ` [PATCH 0/7] rasdaemon: add fixes, database closure and signal handling Shiju Jose
2019-11-20 4:37 ` Mauro Carvalho Chehab
2019-11-13 16:31 ` [PATCH rasdaemon 0/2] rasdaemon: add fix for the sql table Shiju Jose
2019-11-13 16:31 ` [PATCH rasdaemon 1/2] rasdaemon: fix for the ras-record.c:ras_mc_prepare_stmt() failure when new fields added to " Shiju Jose
2019-11-13 16:31 ` [PATCH rasdaemon 2/2] rasdaemon: store PCIe dev name and TLP header for the aer event Shiju Jose
2020-01-15 11:01 ` [RFC PATCH 0/2] ACPI: APEI: Add support to notify the vendor specific HW errors Shiju Jose
2020-01-15 11:01 ` [RFC PATCH 1/2] " Shiju Jose
2020-01-18 15:18 ` kbuild test robot
2020-01-15 11:01 ` [RFC PATCH 2/2] PCI:hip08:Add driver to handle HiSilicon hip08 PCIe controller's errors Shiju Jose
2020-01-15 14:13 ` Bjorn Helgaas
2020-01-17 9:40 ` Shiju Jose
2020-01-24 12:39 ` [PATCH v2 0/2] ACPI: APEI: Add support to notify the vendor specific HW errors Shiju Jose
2020-01-24 12:39 ` [PATCH v2 1/2] " Shiju Jose
2020-01-24 12:39 ` [PATCH v2 2/2] PCI: hip: Add handling of HiSilicon hip PCIe controller's errors Shiju Jose
2020-01-24 14:30 ` Bjorn Helgaas
2020-01-26 18:12 ` kbuild test robot
2020-01-26 18:12 ` kbuild test robot
2020-01-26 18:12 ` [RFC PATCH] PCI: hip: hisi_pcie_sec_type can be static kbuild test robot
2020-01-26 18:12 ` kbuild test robot
2020-02-03 16:51 ` [PATCH v3 0/2] ACPI: APEI: Add support to notify the vendor specific HW errors Shiju Jose
2020-02-03 16:51 ` [PATCH v3 1/2] " Shiju Jose
2020-02-03 16:51 ` [PATCH v3 2/2] PCI: HIP: Add handling of HiSilicon HIP PCIe controller's errors Shiju Jose
2020-02-04 14:31 ` Dan Carpenter
2020-02-04 14:31 ` Dan Carpenter
2020-02-04 14:31 ` Dan Carpenter
2020-02-07 10:31 ` [PATCH v4 0/2] ACPI: APEI: Add support to notify the vendor specific HW errors Shiju Jose
2020-02-07 10:31 ` [PATCH v4 1/2] " Shiju Jose
2020-03-11 17:29 ` James Morse
2020-03-12 12:10 ` Shiju Jose
2020-03-13 15:17 ` James Morse
2020-03-13 17:08 ` Shiju Jose
2020-02-07 10:31 ` [PATCH v4 2/2] PCI: HIP: Add handling of HiSilicon HIP PCIe controller errors Shiju Jose
2020-03-09 9:23 ` [PATCH v4 0/2] ACPI: APEI: Add support to notify the vendor specific HW errors Shiju Jose
2020-03-11 17:27 ` James Morse
2020-03-25 16:42 ` [PATCH v6 0/2] ACPI / " Shiju Jose
2020-03-25 16:42 ` [PATCH v6 1/2] " Shiju Jose
2020-03-27 18:22 ` Borislav Petkov
2020-03-30 10:14 ` Shiju Jose
2020-03-30 10:33 ` Borislav Petkov
2020-03-30 11:55 ` Shiju Jose
2020-03-30 13:42 ` Borislav Petkov
2020-03-30 15:44 ` Shiju Jose
2020-03-31 9:09 ` Borislav Petkov
2020-04-08 9:20 ` Shiju Jose
2020-04-08 10:03 ` James Morse
2020-04-21 13:18 ` Shiju Jose
2020-05-11 11:20 ` Shiju Jose
2020-03-25 16:42 ` [PATCH v6 2/2] PCI: hip: Add handling of HiSilicon HIP PCIe controller errors Shiju Jose
2020-03-27 15:07 ` [PATCH v6 0/2] ACPI / APEI: Add support to notify the vendor specific HW errors Bjorn Helgaas
2020-04-07 12:00 ` [v7 PATCH 0/6] ACPI / APEI: Add support to notify non-fatal " Shiju Jose
2020-04-07 12:00 ` [v7 PATCH 1/6] ACPI / APEI: Add support to queuing up the non-fatal HW errors and notify Shiju Jose
2020-04-08 19:41 ` kbuild test robot
2020-04-08 19:41 ` kbuild test robot
2020-04-08 19:41 ` [RFC PATCH] ACPI / APEI: ghes_gdata_pool_init() can be static kbuild test robot
2020-04-08 19:41 ` kbuild test robot
2020-04-07 12:00 ` [v7 PATCH 2/6] ACPI / APEI: Add callback for memory errors to the GHES notifier Shiju Jose
2020-04-07 12:00 ` [v7 PATCH 3/6] ACPI / APEI: Add callback for AER " Shiju Jose
2020-04-07 12:00 ` [v7 PATCH 4/6] ACPI / APEI: Add callback for ARM HW errors " Shiju Jose
2020-04-07 12:00 ` [v7 PATCH 5/6] ACPI / APEI: Add callback for non-standard " Shiju Jose
2020-04-07 12:00 ` [v7 PATCH 6/6] PCI: hip: Add handling of HiSilicon HIP PCIe controller errors Shiju Jose
2020-04-07 22:03 ` kbuild test robot [this message]
2020-04-07 22:03 ` kbuild test robot
2020-04-21 13:21 ` [RESEND PATCH v7 0/6] ACPI / APEI: Add support to notify non-fatal HW errors Shiju Jose
2020-04-21 13:21 ` [RESEND PATCH v7 1/6] ACPI / APEI: Add support to queuing up the non-fatal HW errors and notify Shiju Jose
2020-04-21 14:12 ` Dan Carpenter
2020-04-21 13:21 ` [RESEND PATCH v7 2/6] ACPI / APEI: Add callback for memory errors to the GHES notifier Shiju Jose
2020-04-21 13:21 ` [RESEND PATCH v7 3/6] ACPI / APEI: Add callback for AER " Shiju Jose
2020-04-21 13:21 ` [RESEND PATCH v7 4/6] ACPI / APEI: Add callback for ARM HW errors " Shiju Jose
2020-04-21 14:14 ` Dan Carpenter
2020-04-21 15:18 ` Shiju Jose
2020-04-21 13:21 ` [RESEND PATCH v7 5/6] ACPI / APEI: Add callback for non-standard " Shiju Jose
2020-04-21 13:21 ` [RESEND PATCH v7 6/6] PCI: hip: Add handling of HiSilicon HIP PCIe controller errors Shiju Jose
2020-04-21 14:20 ` Dan Carpenter
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