* [PATCH 0/3] Enable USB support in IPQ8074
@ 2020-04-10 18:29 Sivaprakash Murugesan
2020-04-10 18:29 ` [PATCH 1/3] dt-bindings: phy: qcom,qmp: Add ipq8074 usb dt bindings Sivaprakash Murugesan
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Sivaprakash Murugesan @ 2020-04-10 18:29 UTC (permalink / raw)
To: agross, bjorn.andersson, kishon, robh+dt, linux-arm-msm,
linux-kernel, devicetree
Cc: Sivaprakash Murugesan
IPQ8074 has two super speed USB ports, with QMP and QUSB2 PHYs.
This patch set enables the USB PHYs and USB dwc3 in IPQ8074.
This patch set depends on Sandeep's QMP PHY binding patch
https://patchwork.ozlabs.org/patch/1265442/
Sivaprakash Murugesan (3):
dt-bindings: phy: qcom,qmp: Add ipq8074 usb dt bindings
phy: qcom-qmp: Add USB QMP PHY support for IPQ8074
arm64: dts: ipq8074: enable USB support
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 +
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 24 +++
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 168 +++++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.c | 102 +++++++++++++
4 files changed, 296 insertions(+)
--
2.7.4
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 1/3] dt-bindings: phy: qcom,qmp: Add ipq8074 usb dt bindings 2020-04-10 18:29 [PATCH 0/3] Enable USB support in IPQ8074 Sivaprakash Murugesan @ 2020-04-10 18:29 ` Sivaprakash Murugesan 2020-04-10 22:05 ` Bjorn Andersson 2020-04-10 18:29 ` [PATCH 2/3] phy: qcom-qmp: Add USB QMP PHY support for IPQ8074 Sivaprakash Murugesan 2020-04-10 18:29 ` [PATCH 3/3] arm64: dts: ipq8074: enable USB support Sivaprakash Murugesan 2 siblings, 1 reply; 9+ messages in thread From: Sivaprakash Murugesan @ 2020-04-10 18:29 UTC (permalink / raw) To: agross, bjorn.andersson, kishon, robh+dt, linux-arm-msm, linux-kernel, devicetree Cc: Sivaprakash Murugesan Add ipq8074 qmp phy device compatible for usb super speed usb support. Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> --- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index 18a8985..d60c845 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -18,6 +18,7 @@ properties: compatible: enum: - qcom,ipq8074-qmp-pcie-phy + - qcom,ipq8074-qmp-usb-phy - qcom,msm8996-qmp-pcie-phy - qcom,msm8996-qmp-ufs-phy - qcom,msm8996-qmp-usb3-phy @@ -166,6 +167,7 @@ allOf: compatible: contains: enum: + - qcom,ipq8074-qmp-usb3-phy - qcom,msm8996-qmp-usb3-phy - qcom,msm8998-qmp-pcie-phy - qcom,msm8998-qmp-usb3-phy -- 2.7.4 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] dt-bindings: phy: qcom,qmp: Add ipq8074 usb dt bindings 2020-04-10 18:29 ` [PATCH 1/3] dt-bindings: phy: qcom,qmp: Add ipq8074 usb dt bindings Sivaprakash Murugesan @ 2020-04-10 22:05 ` Bjorn Andersson 2020-04-11 0:45 ` Sivaprakash Murugesan 0 siblings, 1 reply; 9+ messages in thread From: Bjorn Andersson @ 2020-04-10 22:05 UTC (permalink / raw) To: Sivaprakash Murugesan Cc: agross, kishon, robh+dt, linux-arm-msm, linux-kernel, devicetree On Fri 10 Apr 11:29 PDT 2020, Sivaprakash Murugesan wrote: > Add ipq8074 qmp phy device compatible for usb super speed usb support. > > Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> > --- > Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml > index 18a8985..d60c845 100644 > --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml > +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml > @@ -18,6 +18,7 @@ properties: > compatible: > enum: > - qcom,ipq8074-qmp-pcie-phy > + - qcom,ipq8074-qmp-usb-phy I believe you're missing a "3" here. Regards, Bjorn > - qcom,msm8996-qmp-pcie-phy > - qcom,msm8996-qmp-ufs-phy > - qcom,msm8996-qmp-usb3-phy > @@ -166,6 +167,7 @@ allOf: > compatible: > contains: > enum: > + - qcom,ipq8074-qmp-usb3-phy > - qcom,msm8996-qmp-usb3-phy > - qcom,msm8998-qmp-pcie-phy > - qcom,msm8998-qmp-usb3-phy > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] dt-bindings: phy: qcom,qmp: Add ipq8074 usb dt bindings 2020-04-10 22:05 ` Bjorn Andersson @ 2020-04-11 0:45 ` Sivaprakash Murugesan 0 siblings, 0 replies; 9+ messages in thread From: Sivaprakash Murugesan @ 2020-04-11 0:45 UTC (permalink / raw) To: Bjorn Andersson Cc: agross, kishon, robh+dt, linux-arm-msm, linux-kernel, devicetree Hi Bjorn, On 4/11/2020 3:35 AM, Bjorn Andersson wrote: > On Fri 10 Apr 11:29 PDT 2020, Sivaprakash Murugesan wrote: > >> Add ipq8074 qmp phy device compatible for usb super speed usb support. >> >> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> >> --- >> Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml >> index 18a8985..d60c845 100644 >> --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml >> +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml >> @@ -18,6 +18,7 @@ properties: >> compatible: >> enum: >> - qcom,ipq8074-qmp-pcie-phy >> + - qcom,ipq8074-qmp-usb-phy > I believe you're missing a "3" here. Yes. Will correct it in next patch set. > Regards, > Bjorn > ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/3] phy: qcom-qmp: Add USB QMP PHY support for IPQ8074 2020-04-10 18:29 [PATCH 0/3] Enable USB support in IPQ8074 Sivaprakash Murugesan 2020-04-10 18:29 ` [PATCH 1/3] dt-bindings: phy: qcom,qmp: Add ipq8074 usb dt bindings Sivaprakash Murugesan @ 2020-04-10 18:29 ` Sivaprakash Murugesan 2020-04-10 22:18 ` Bjorn Andersson 2020-04-10 18:29 ` [PATCH 3/3] arm64: dts: ipq8074: enable USB support Sivaprakash Murugesan 2 siblings, 1 reply; 9+ messages in thread From: Sivaprakash Murugesan @ 2020-04-10 18:29 UTC (permalink / raw) To: agross, bjorn.andersson, kishon, robh+dt, linux-arm-msm, linux-kernel, devicetree Cc: Sivaprakash Murugesan, Balaji Prakash J Add QMP USB PHY found in IPQ8074 Co-developed-by: Balaji Prakash J <bjagadee@codeaurora.org> Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> --- drivers/phy/qualcomm/phy-qcom-qmp.c | 102 ++++++++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index c190406..8e9a8a4 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -188,6 +188,81 @@ static const unsigned int sm8150_ufsphy_regs_layout[] = { [QPHY_SW_RESET] = QPHY_V4_SW_RESET, }; +static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), + /* PLL and Loop filter settings */ + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), + /* SSC settings */ + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), +}; + +static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0), +}; + +static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), +}; + static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), @@ -1467,6 +1542,30 @@ static const char * const qmp_phy_vreg_l[] = { "vdda-phy", "vdda-pll", }; +static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = ipq8074_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl), + .tx_tbl = msm8996_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), + .rx_tbl = ipq8074_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl), + .pcs_tbl = ipq8074_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl), + .clk_list = msm8996_phy_clk_l, + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = usb3phy_regs_layout, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, +}; + static const struct qmp_phy_cfg msm8996_pciephy_cfg = { .type = PHY_TYPE_PCIE, .nlanes = 3, @@ -2498,6 +2597,9 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id) static const struct of_device_id qcom_qmp_phy_of_match_table[] = { { + .compatible = "qcom,ipq8074-qmp-usb3-phy", + .data = &ipq8074_usb3phy_cfg, + }, { .compatible = "qcom,msm8996-qmp-pcie-phy", .data = &msm8996_pciephy_cfg, }, { -- 2.7.4 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] phy: qcom-qmp: Add USB QMP PHY support for IPQ8074 2020-04-10 18:29 ` [PATCH 2/3] phy: qcom-qmp: Add USB QMP PHY support for IPQ8074 Sivaprakash Murugesan @ 2020-04-10 22:18 ` Bjorn Andersson 0 siblings, 0 replies; 9+ messages in thread From: Bjorn Andersson @ 2020-04-10 22:18 UTC (permalink / raw) To: Sivaprakash Murugesan Cc: agross, kishon, robh+dt, linux-arm-msm, linux-kernel, devicetree, Balaji Prakash J On Fri 10 Apr 11:29 PDT 2020, Sivaprakash Murugesan wrote: > Add QMP USB PHY found in IPQ8074 > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Co-developed-by: Balaji Prakash J <bjagadee@codeaurora.org> > Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org> > Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> > --- > drivers/phy/qualcomm/phy-qcom-qmp.c | 102 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 102 insertions(+) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c > index c190406..8e9a8a4 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c > @@ -188,6 +188,81 @@ static const unsigned int sm8150_ufsphy_regs_layout[] = { > [QPHY_SW_RESET] = QPHY_V4_SW_RESET, > }; > > +static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = { > + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), > + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), > + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), > + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), > + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), > + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), > + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), > + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), > + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), > + /* PLL and Loop filter settings */ > + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), > + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), > + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), > + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), > + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), > + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), > + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), > + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), > + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), > + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), > + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), > + /* SSC settings */ > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), > +}; > + > +static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = { > + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06), > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), > + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), > + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), > + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0), > +}; > + > +static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = { > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), > +}; > + > static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = { > QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), > QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), > @@ -1467,6 +1542,30 @@ static const char * const qmp_phy_vreg_l[] = { > "vdda-phy", "vdda-pll", > }; > > +static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { > + .type = PHY_TYPE_USB3, > + .nlanes = 1, > + > + .serdes_tbl = ipq8074_usb3_serdes_tbl, > + .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl), > + .tx_tbl = msm8996_usb3_tx_tbl, > + .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), > + .rx_tbl = ipq8074_usb3_rx_tbl, > + .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl), > + .pcs_tbl = ipq8074_usb3_pcs_tbl, > + .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl), > + .clk_list = msm8996_phy_clk_l, > + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), > + .reset_list = msm8996_usb3phy_reset_l, > + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), > + .vreg_list = qmp_phy_vreg_l, > + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), > + .regs = usb3phy_regs_layout, > + > + .start_ctrl = SERDES_START | PCS_START, > + .pwrdn_ctrl = SW_PWRDN, > +}; > + > static const struct qmp_phy_cfg msm8996_pciephy_cfg = { > .type = PHY_TYPE_PCIE, > .nlanes = 3, > @@ -2498,6 +2597,9 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id) > > static const struct of_device_id qcom_qmp_phy_of_match_table[] = { > { > + .compatible = "qcom,ipq8074-qmp-usb3-phy", > + .data = &ipq8074_usb3phy_cfg, > + }, { > .compatible = "qcom,msm8996-qmp-pcie-phy", > .data = &msm8996_pciephy_cfg, > }, { > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 3/3] arm64: dts: ipq8074: enable USB support 2020-04-10 18:29 [PATCH 0/3] Enable USB support in IPQ8074 Sivaprakash Murugesan 2020-04-10 18:29 ` [PATCH 1/3] dt-bindings: phy: qcom,qmp: Add ipq8074 usb dt bindings Sivaprakash Murugesan 2020-04-10 18:29 ` [PATCH 2/3] phy: qcom-qmp: Add USB QMP PHY support for IPQ8074 Sivaprakash Murugesan @ 2020-04-10 18:29 ` Sivaprakash Murugesan 2020-04-10 22:17 ` Bjorn Andersson 2 siblings, 1 reply; 9+ messages in thread From: Sivaprakash Murugesan @ 2020-04-10 18:29 UTC (permalink / raw) To: agross, bjorn.andersson, kishon, robh+dt, linux-arm-msm, linux-kernel, devicetree Cc: Sivaprakash Murugesan, Balaji Prakash J IPQ8074 has two super speed usb ports, add phy and dwc3 nodes to enable them. Co-developed-by: Balaji Prakash J <bjagadee@codeaurora.org> Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> --- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 24 +++++ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 168 ++++++++++++++++++++++++++++++ 2 files changed, 192 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts index 70be3f9..dd27d84 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts @@ -26,6 +26,22 @@ }; soc { + ssphy@58000 { + status = "ok"; + }; + + qusb@59000 { + status = "ok"; + }; + + ssphy@78000 { + status = "ok"; + }; + + qusb@79000 { + status = "ok"; + }; + serial@78b3000 { status = "ok"; }; @@ -65,6 +81,14 @@ }; }; + usb3@8A00000 { + status = "ok"; + }; + + usb3@8C00000 { + status = "ok"; + }; + phy@86000 { status = "ok"; }; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 2b31823..47bb9ad 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -16,6 +16,92 @@ ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; + ssphy_1: ssphy@58000 { + compatible = "qcom,ipq8074-qmp-usb3-phy"; + reg = <0x00058000 0x1c4>; + status = "disabled"; + #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB1_AUX_CLK>, + <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, + <&xo>; + clock-names = "aux", "cfg_ahb", "ref"; + + resets = <&gcc GCC_USB1_PHY_BCR>, + <&gcc GCC_USB3PHY_1_PHY_BCR>; + reset-names = "phy","common"; + + usb1_ssphy: lane@58200 { + reg = <0x00058200 0x130>, /* Tx */ + <0x00058400 0x200>, /* Rx */ + <0x00058800 0x1F8>, /* PCS */ + <0x00058600 0x044>; /* PCS misc */ + #phy-cells = <0>; + clocks = <&gcc GCC_USB1_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "gcc_usb1_pipe_clk_src"; + }; + }; + + qusb_phy_1: qusb@59000 { + compatible = "qcom,msm8996-qusb2-phy"; + reg = <0x00059000 0x180>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, + <&xo>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2_1_PHY_BCR>; + }; + + ssphy_0: ssphy@78000 { + compatible = "qcom,ipq8074-qmp-usb3-phy"; + reg = <0x00078000 0x1c4>; + status = "disabled"; + #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB0_AUX_CLK>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&xo>; + clock-names = "aux", "cfg_ahb", "ref"; + + resets = <&gcc GCC_USB0_PHY_BCR>, + <&gcc GCC_USB3PHY_0_PHY_BCR>; + reset-names = "phy","common"; + + usb0_ssphy: lane@78200 { + reg = <0x00078200 0x130>, /* Tx */ + <0x00078400 0x200>, /* Rx */ + <0x00078800 0x1F8>, /* PCS */ + <0x00078600 0x044>; /* PCS misc */ + #phy-cells = <0>; + clocks = <&gcc GCC_USB0_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "gcc_usb0_pipe_clk_src"; + }; + }; + + qusb_phy_0: qusb@79000 { + compatible = "qcom,msm8996-qusb2-phy"; + reg = <0x00079000 0x180>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&xo>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq8074-pinctrl"; reg = <0x1000000 0x300000>; @@ -272,6 +358,88 @@ status = "disabled"; }; + usb3_0: usb3@8A00000 { + compatible = "qcom,dwc3"; + reg = <0x08af8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, + <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_SLEEP_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + clock-names = "sys_noc_axi", + "master", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, + <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + assigned-clock-rates = <133330000>, + <133330000>, + <19200000>; + + resets = <&gcc GCC_USB0_BCR>; + status = "disabled"; + + dwc_0: dwc3@8A00000 { + compatible = "snps,dwc3"; + reg = <0x8A00000 0xcd00>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + phys = <&qusb_phy_0>, <&usb0_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + dr_mode = "host"; + }; + }; + + usb3_1: usb3@8C00000 { + compatible = "qcom,dwc3"; + reg = <0x08cf8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, + <&gcc GCC_USB1_MASTER_CLK>, + <&gcc GCC_USB1_SLEEP_CLK>, + <&gcc GCC_USB1_MOCK_UTMI_CLK>; + clock-names = "sys_noc_axi", + "master", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, + <&gcc GCC_USB1_MASTER_CLK>, + <&gcc GCC_USB1_MOCK_UTMI_CLK>; + assigned-clock-rates = <133330000>, + <133330000>, + <19200000>; + + resets = <&gcc GCC_USB1_BCR>; + status = "disabled"; + + dwc_1: dwc3@8C00000 { + compatible = "snps,dwc3"; + reg = <0x8C00000 0xcd00>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + phys = <&qusb_phy_1>, <&usb1_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + dr_mode = "host"; + }; + }; + pcie_phy0: phy@86000 { compatible = "qcom,ipq8074-qmp-pcie-phy"; reg = <0x86000 0x1000>; -- 2.7.4 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] arm64: dts: ipq8074: enable USB support 2020-04-10 18:29 ` [PATCH 3/3] arm64: dts: ipq8074: enable USB support Sivaprakash Murugesan @ 2020-04-10 22:17 ` Bjorn Andersson 2020-04-11 0:54 ` Sivaprakash Murugesan 0 siblings, 1 reply; 9+ messages in thread From: Bjorn Andersson @ 2020-04-10 22:17 UTC (permalink / raw) To: Sivaprakash Murugesan Cc: agross, kishon, robh+dt, linux-arm-msm, linux-kernel, devicetree, Balaji Prakash J On Fri 10 Apr 11:29 PDT 2020, Sivaprakash Murugesan wrote: > IPQ8074 has two super speed usb ports, add phy and dwc3 nodes > to enable them. > Thanks Sivaprakash, your patch looks good, just some comments on the style below. > Co-developed-by: Balaji Prakash J <bjagadee@codeaurora.org> > Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org> > Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 24 +++++ > arch/arm64/boot/dts/qcom/ipq8074.dtsi | 168 ++++++++++++++++++++++++++++++ > 2 files changed, 192 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts > index 70be3f9..dd27d84 100644 > --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts > +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts > @@ -26,6 +26,22 @@ > }; > > soc { > + ssphy@58000 { Please reference these by label, like we do in e.g. sdm845-mtp.dts. > + status = "ok"; > + }; > + > + qusb@59000 { > + status = "ok"; > + }; > + > + ssphy@78000 { > + status = "ok"; > + }; > + > + qusb@79000 { > + status = "ok"; > + }; > + > serial@78b3000 { > status = "ok"; > }; > @@ -65,6 +81,14 @@ > }; > }; > > + usb3@8A00000 { > + status = "ok"; > + }; > + > + usb3@8C00000 { > + status = "ok"; > + }; > + > phy@86000 { > status = "ok"; > }; > diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi > index 2b31823..47bb9ad 100644 > --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi > @@ -16,6 +16,92 @@ > ranges = <0 0 0 0xffffffff>; > compatible = "simple-bus"; > > + ssphy_1: ssphy@58000 { Please use the generic name of "phy" here (i.e. ssphy_1: phy@58000 {) > + compatible = "qcom,ipq8074-qmp-usb3-phy"; > + reg = <0x00058000 0x1c4>; > + status = "disabled"; > + #clock-cells = <1>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + clocks = <&gcc GCC_USB1_AUX_CLK>, > + <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, > + <&xo>; > + clock-names = "aux", "cfg_ahb", "ref"; > + > + resets = <&gcc GCC_USB1_PHY_BCR>, > + <&gcc GCC_USB3PHY_1_PHY_BCR>; > + reset-names = "phy","common"; > + > + usb1_ssphy: lane@58200 { > + reg = <0x00058200 0x130>, /* Tx */ > + <0x00058400 0x200>, /* Rx */ > + <0x00058800 0x1F8>, /* PCS */ > + <0x00058600 0x044>; /* PCS misc */ > + #phy-cells = <0>; > + clocks = <&gcc GCC_USB1_PIPE_CLK>; > + clock-names = "pipe0"; > + clock-output-names = "gcc_usb1_pipe_clk_src"; > + }; > + }; > + > + qusb_phy_1: qusb@59000 { phy@ > + compatible = "qcom,msm8996-qusb2-phy"; Please add and use a ipq8074 compatible to the driver (.data can point to msm8996_phy_cfg still). > + reg = <0x00059000 0x180>; > + status = "disabled"; > + #phy-cells = <0>; > + > + clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, > + <&xo>; > + clock-names = "cfg_ahb", "ref"; > + > + resets = <&gcc GCC_QUSB2_1_PHY_BCR>; > + }; > + > + ssphy_0: ssphy@78000 { phy@ > + compatible = "qcom,ipq8074-qmp-usb3-phy"; > + reg = <0x00078000 0x1c4>; > + status = "disabled"; > + #clock-cells = <1>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + clocks = <&gcc GCC_USB0_AUX_CLK>, > + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > + <&xo>; > + clock-names = "aux", "cfg_ahb", "ref"; > + > + resets = <&gcc GCC_USB0_PHY_BCR>, > + <&gcc GCC_USB3PHY_0_PHY_BCR>; > + reset-names = "phy","common"; > + > + usb0_ssphy: lane@78200 { > + reg = <0x00078200 0x130>, /* Tx */ > + <0x00078400 0x200>, /* Rx */ > + <0x00078800 0x1F8>, /* PCS */ > + <0x00078600 0x044>; /* PCS misc */ > + #phy-cells = <0>; > + clocks = <&gcc GCC_USB0_PIPE_CLK>; > + clock-names = "pipe0"; > + clock-output-names = "gcc_usb0_pipe_clk_src"; > + }; > + }; > + > + qusb_phy_0: qusb@79000 { phy@ > + compatible = "qcom,msm8996-qusb2-phy"; > + reg = <0x00079000 0x180>; > + status = "disabled"; > + #phy-cells = <0>; > + > + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > + <&xo>; > + clock-names = "cfg_ahb", "ref"; > + > + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; > + }; > + > tlmm: pinctrl@1000000 { > compatible = "qcom,ipq8074-pinctrl"; > reg = <0x1000000 0x300000>; > @@ -272,6 +358,88 @@ > status = "disabled"; > }; > > + usb3_0: usb3@8A00000 { usb@ and please lower case and make sure the unit address matches the reg. > + compatible = "qcom,dwc3"; > + reg = <0x08af8800 0x400>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, > + <&gcc GCC_USB0_MASTER_CLK>, > + <&gcc GCC_USB0_SLEEP_CLK>, > + <&gcc GCC_USB0_MOCK_UTMI_CLK>; > + clock-names = "sys_noc_axi", > + "master", > + "sleep", > + "mock_utmi"; > + > + assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, > + <&gcc GCC_USB0_MASTER_CLK>, > + <&gcc GCC_USB0_MOCK_UTMI_CLK>; > + assigned-clock-rates = <133330000>, > + <133330000>, > + <19200000>; > + > + resets = <&gcc GCC_USB0_BCR>; > + status = "disabled"; > + > + dwc_0: dwc3@8A00000 { Please lowercase the address > + compatible = "snps,dwc3"; > + reg = <0x8A00000 0xcd00>; Ditto. > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&qusb_phy_0>, <&usb0_ssphy>; > + phy-names = "usb2-phy", "usb3-phy"; > + tx-fifo-resize; > + snps,is-utmi-l1-suspend; > + snps,hird-threshold = /bits/ 8 <0x0>; > + snps,dis_u2_susphy_quirk; > + snps,dis_u3_susphy_quirk; > + dr_mode = "host"; > + }; > + }; > + > + usb3_1: usb3@8C00000 { usb@, lowercase and match reg. > + compatible = "qcom,dwc3"; > + reg = <0x08cf8800 0x400>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, > + <&gcc GCC_USB1_MASTER_CLK>, > + <&gcc GCC_USB1_SLEEP_CLK>, > + <&gcc GCC_USB1_MOCK_UTMI_CLK>; > + clock-names = "sys_noc_axi", > + "master", > + "sleep", > + "mock_utmi"; > + > + assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, > + <&gcc GCC_USB1_MASTER_CLK>, > + <&gcc GCC_USB1_MOCK_UTMI_CLK>; > + assigned-clock-rates = <133330000>, > + <133330000>, > + <19200000>; > + > + resets = <&gcc GCC_USB1_BCR>; > + status = "disabled"; > + > + dwc_1: dwc3@8C00000 { Please lowercase > + compatible = "snps,dwc3"; > + reg = <0x8C00000 0xcd00>; Ditto. > + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&qusb_phy_1>, <&usb1_ssphy>; > + phy-names = "usb2-phy", "usb3-phy"; > + tx-fifo-resize; > + snps,is-utmi-l1-suspend; > + snps,hird-threshold = /bits/ 8 <0x0>; > + snps,dis_u2_susphy_quirk; > + snps,dis_u3_susphy_quirk; > + dr_mode = "host"; > + }; > + }; > + > pcie_phy0: phy@86000 { > compatible = "qcom,ipq8074-qmp-pcie-phy"; > reg = <0x86000 0x1000>; If you could send a separate patch (after this is merged is okay) that sort the nodes in this file by address, it would be much appreciated. Regards, Bjorn > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] arm64: dts: ipq8074: enable USB support 2020-04-10 22:17 ` Bjorn Andersson @ 2020-04-11 0:54 ` Sivaprakash Murugesan 0 siblings, 0 replies; 9+ messages in thread From: Sivaprakash Murugesan @ 2020-04-11 0:54 UTC (permalink / raw) To: Bjorn Andersson Cc: agross, kishon, robh+dt, linux-arm-msm, linux-kernel, devicetree, Balaji Prakash J Hi Bjorn, On 4/11/2020 3:47 AM, Bjorn Andersson wrote: > On Fri 10 Apr 11:29 PDT 2020, Sivaprakash Murugesan wrote: > >> IPQ8074 has two super speed usb ports, add phy and dwc3 nodes >> to enable them. >> > Thanks Sivaprakash, your patch looks good, just some comments on the > style below. > >> Co-developed-by: Balaji Prakash J <bjagadee@codeaurora.org> >> Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org> >> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> >> --- >> arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 24 +++++ >> arch/arm64/boot/dts/qcom/ipq8074.dtsi | 168 ++++++++++++++++++++++++++++++ >> 2 files changed, 192 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts >> index 70be3f9..dd27d84 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts >> +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts >> @@ -26,6 +26,22 @@ >> }; >> >> soc { >> + ssphy@58000 { > Please reference these by label, like we do in e.g. sdm845-mtp.dts. ok. > >> + status = "ok"; >> + }; >> + >> + qusb@59000 { >> + status = "ok"; >> + }; >> + >> + ssphy@78000 { >> + status = "ok"; >> + }; >> + >> + qusb@79000 { >> + status = "ok"; >> + }; >> + >> serial@78b3000 { >> status = "ok"; >> }; >> @@ -65,6 +81,14 @@ >> }; >> }; >> >> + usb3@8A00000 { >> + status = "ok"; >> + }; >> + >> + usb3@8C00000 { >> + status = "ok"; >> + }; >> + >> phy@86000 { >> status = "ok"; >> }; >> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi >> index 2b31823..47bb9ad 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi >> @@ -16,6 +16,92 @@ >> ranges = <0 0 0 0xffffffff>; >> compatible = "simple-bus"; >> >> + ssphy_1: ssphy@58000 { > Please use the generic name of "phy" here (i.e. ssphy_1: phy@58000 {) ok. > >> + compatible = "qcom,ipq8074-qmp-usb3-phy"; >> + reg = <0x00058000 0x1c4>; >> + status = "disabled"; >> + #clock-cells = <1>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + >> + clocks = <&gcc GCC_USB1_AUX_CLK>, >> + <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, >> + <&xo>; >> + clock-names = "aux", "cfg_ahb", "ref"; >> + >> + resets = <&gcc GCC_USB1_PHY_BCR>, >> + <&gcc GCC_USB3PHY_1_PHY_BCR>; >> + reset-names = "phy","common"; >> + >> + usb1_ssphy: lane@58200 { >> + reg = <0x00058200 0x130>, /* Tx */ >> + <0x00058400 0x200>, /* Rx */ >> + <0x00058800 0x1F8>, /* PCS */ >> + <0x00058600 0x044>; /* PCS misc */ >> + #phy-cells = <0>; >> + clocks = <&gcc GCC_USB1_PIPE_CLK>; >> + clock-names = "pipe0"; >> + clock-output-names = "gcc_usb1_pipe_clk_src"; >> + }; >> + }; >> + >> + qusb_phy_1: qusb@59000 { > phy@ ok. > >> + compatible = "qcom,msm8996-qusb2-phy"; > Please add and use a ipq8074 compatible to the driver (.data can point > to msm8996_phy_cfg still). sure, will do. > >> + reg = <0x00059000 0x180>; >> + status = "disabled"; >> + #phy-cells = <0>; >> + >> + clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, >> + <&xo>; >> + clock-names = "cfg_ahb", "ref"; >> + >> + resets = <&gcc GCC_QUSB2_1_PHY_BCR>; >> + }; >> + >> + ssphy_0: ssphy@78000 { > phy@ ok. >> + compatible = "qcom,ipq8074-qmp-usb3-phy"; >> + reg = <0x00078000 0x1c4>; >> + status = "disabled"; >> + #clock-cells = <1>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + >> + clocks = <&gcc GCC_USB0_AUX_CLK>, >> + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, >> + <&xo>; >> + clock-names = "aux", "cfg_ahb", "ref"; >> + >> + resets = <&gcc GCC_USB0_PHY_BCR>, >> + <&gcc GCC_USB3PHY_0_PHY_BCR>; >> + reset-names = "phy","common"; >> + >> + usb0_ssphy: lane@78200 { >> + reg = <0x00078200 0x130>, /* Tx */ >> + <0x00078400 0x200>, /* Rx */ >> + <0x00078800 0x1F8>, /* PCS */ >> + <0x00078600 0x044>; /* PCS misc */ >> + #phy-cells = <0>; >> + clocks = <&gcc GCC_USB0_PIPE_CLK>; >> + clock-names = "pipe0"; >> + clock-output-names = "gcc_usb0_pipe_clk_src"; >> + }; >> + }; >> + >> + qusb_phy_0: qusb@79000 { > phy@ ok. > >> + compatible = "qcom,msm8996-qusb2-phy"; >> + reg = <0x00079000 0x180>; >> + status = "disabled"; >> + #phy-cells = <0>; >> + >> + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, >> + <&xo>; >> + clock-names = "cfg_ahb", "ref"; >> + >> + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; >> + }; >> + >> tlmm: pinctrl@1000000 { >> compatible = "qcom,ipq8074-pinctrl"; >> reg = <0x1000000 0x300000>; >> @@ -272,6 +358,88 @@ >> status = "disabled"; >> }; >> >> + usb3_0: usb3@8A00000 { > usb@ and please lower case and make sure the unit address matches the > reg. ok. > >> + compatible = "qcom,dwc3"; >> + reg = <0x08af8800 0x400>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + >> + clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, >> + <&gcc GCC_USB0_MASTER_CLK>, >> + <&gcc GCC_USB0_SLEEP_CLK>, >> + <&gcc GCC_USB0_MOCK_UTMI_CLK>; >> + clock-names = "sys_noc_axi", >> + "master", >> + "sleep", >> + "mock_utmi"; >> + >> + assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, >> + <&gcc GCC_USB0_MASTER_CLK>, >> + <&gcc GCC_USB0_MOCK_UTMI_CLK>; >> + assigned-clock-rates = <133330000>, >> + <133330000>, >> + <19200000>; >> + >> + resets = <&gcc GCC_USB0_BCR>; >> + status = "disabled"; >> + >> + dwc_0: dwc3@8A00000 { > Please lowercase the address ok. > >> + compatible = "snps,dwc3"; >> + reg = <0x8A00000 0xcd00>; > Ditto. ok. > >> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; >> + phys = <&qusb_phy_0>, <&usb0_ssphy>; >> + phy-names = "usb2-phy", "usb3-phy"; >> + tx-fifo-resize; >> + snps,is-utmi-l1-suspend; >> + snps,hird-threshold = /bits/ 8 <0x0>; >> + snps,dis_u2_susphy_quirk; >> + snps,dis_u3_susphy_quirk; >> + dr_mode = "host"; >> + }; >> + }; >> + >> + usb3_1: usb3@8C00000 { > usb@, lowercase and match reg. ok > >> + compatible = "qcom,dwc3"; >> + reg = <0x08cf8800 0x400>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + >> + clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, >> + <&gcc GCC_USB1_MASTER_CLK>, >> + <&gcc GCC_USB1_SLEEP_CLK>, >> + <&gcc GCC_USB1_MOCK_UTMI_CLK>; >> + clock-names = "sys_noc_axi", >> + "master", >> + "sleep", >> + "mock_utmi"; >> + >> + assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, >> + <&gcc GCC_USB1_MASTER_CLK>, >> + <&gcc GCC_USB1_MOCK_UTMI_CLK>; >> + assigned-clock-rates = <133330000>, >> + <133330000>, >> + <19200000>; >> + >> + resets = <&gcc GCC_USB1_BCR>; >> + status = "disabled"; >> + >> + dwc_1: dwc3@8C00000 { > Please lowercase ok > >> + compatible = "snps,dwc3"; >> + reg = <0x8C00000 0xcd00>; > Ditto. ok > >> + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; >> + phys = <&qusb_phy_1>, <&usb1_ssphy>; >> + phy-names = "usb2-phy", "usb3-phy"; >> + tx-fifo-resize; >> + snps,is-utmi-l1-suspend; >> + snps,hird-threshold = /bits/ 8 <0x0>; >> + snps,dis_u2_susphy_quirk; >> + snps,dis_u3_susphy_quirk; >> + dr_mode = "host"; >> + }; >> + }; >> + >> pcie_phy0: phy@86000 { >> compatible = "qcom,ipq8074-qmp-pcie-phy"; >> reg = <0x86000 0x1000>; > If you could send a separate patch (after this is merged is okay) that > sort the nodes in this file by address, it would be much appreciated. sure. Based on the comments above the dts needs clean. will send a separate patch for it. > > Regards, > Bjorn Thanks, Siva >> -- >> 2.7.4 >> ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2020-04-11 0:55 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-04-10 18:29 [PATCH 0/3] Enable USB support in IPQ8074 Sivaprakash Murugesan 2020-04-10 18:29 ` [PATCH 1/3] dt-bindings: phy: qcom,qmp: Add ipq8074 usb dt bindings Sivaprakash Murugesan 2020-04-10 22:05 ` Bjorn Andersson 2020-04-11 0:45 ` Sivaprakash Murugesan 2020-04-10 18:29 ` [PATCH 2/3] phy: qcom-qmp: Add USB QMP PHY support for IPQ8074 Sivaprakash Murugesan 2020-04-10 22:18 ` Bjorn Andersson 2020-04-10 18:29 ` [PATCH 3/3] arm64: dts: ipq8074: enable USB support Sivaprakash Murugesan 2020-04-10 22:17 ` Bjorn Andersson 2020-04-11 0:54 ` Sivaprakash Murugesan
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