From: Will Deacon <will@kernel.org>
To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu
Cc: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>,
kernel-team@android.com,
Anshuman Khandual <anshuman.khandual@arm.com>,
Marc Zyngier <maz@kernel.org>,
linux-kernel@vger.kernel.org,
Doug Anderson <dianders@chromium.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>
Subject: [PATCH 3/8] arm64: cpufeature: Add CPU capability for AArch32 EL1 support
Date: Tue, 14 Apr 2020 22:31:09 +0100 [thread overview]
Message-ID: <20200414213114.2378-4-will@kernel.org> (raw)
In-Reply-To: <20200414213114.2378-1-will@kernel.org>
Although we emit a "SANITY CHECK" warning and taint the kernel if we
detect a CPU mismatch for AArch32 support at EL1, we still online the
CPU with disastrous consequences for any running 32-bit VMs.
Introduce a capability for AArch32 support at EL1 so that late onlining
of incompatible CPUs is forbidden.
Signed-off-by: Will Deacon <will@kernel.org>
---
arch/arm64/include/asm/cpucaps.h | 3 ++-
arch/arm64/include/asm/sysreg.h | 1 +
arch/arm64/kernel/cpufeature.c | 12 ++++++++++++
arch/arm64/kvm/reset.c | 12 ++----------
4 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
index 8eb5a088ae65..c54c674e6c21 100644
--- a/arch/arm64/include/asm/cpucaps.h
+++ b/arch/arm64/include/asm/cpucaps.h
@@ -61,7 +61,8 @@
#define ARM64_HAS_AMU_EXTN 51
#define ARM64_HAS_ADDRESS_AUTH 52
#define ARM64_HAS_GENERIC_AUTH 53
+#define ARM64_HAS_32BIT_EL1 54
-#define ARM64_NCAPS 54
+#define ARM64_NCAPS 55
#endif /* __ASM_CPUCAPS_H */
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 139cd24c181b..3d8e2f0347c4 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -653,6 +653,7 @@
#define ID_AA64PFR0_ASIMD_NI 0xf
#define ID_AA64PFR0_ASIMD_SUPPORTED 0x0
#define ID_AA64PFR0_EL1_64BIT_ONLY 0x1
+#define ID_AA64PFR0_EL1_32BIT_64BIT 0x2
#define ID_AA64PFR0_EL0_64BIT_ONLY 0x1
#define ID_AA64PFR0_EL0_32BIT_64BIT 0x2
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index b143f8bc6c52..838fe5cc8d7e 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1535,6 +1535,18 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.field_pos = ID_AA64PFR0_EL0_SHIFT,
.min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
},
+#ifdef CONFIG_KVM
+ {
+ .desc = "32-bit EL1 Support",
+ .capability = ARM64_HAS_32BIT_EL1,
+ .type = ARM64_CPUCAP_SYSTEM_FEATURE,
+ .matches = has_cpuid_feature,
+ .sys_reg = SYS_ID_AA64PFR0_EL1,
+ .sign = FTR_UNSIGNED,
+ .field_pos = ID_AA64PFR0_EL1_SHIFT,
+ .min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT,
+ },
+#endif
{
.desc = "Kernel page table isolation (KPTI)",
.capability = ARM64_UNMAP_KERNEL_AT_EL0,
diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
index 30b7ea680f66..102e5c4e01a0 100644
--- a/arch/arm64/kvm/reset.c
+++ b/arch/arm64/kvm/reset.c
@@ -46,14 +46,6 @@ static const struct kvm_regs default_regs_reset32 = {
PSR_AA32_I_BIT | PSR_AA32_F_BIT),
};
-static bool cpu_has_32bit_el1(void)
-{
- u64 pfr0;
-
- pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
- return !!(pfr0 & 0x20);
-}
-
/**
* kvm_arch_vm_ioctl_check_extension
*
@@ -66,7 +58,7 @@ int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext)
switch (ext) {
case KVM_CAP_ARM_EL1_32BIT:
- r = cpu_has_32bit_el1();
+ r = cpus_have_const_cap(ARM64_HAS_32BIT_EL1);
break;
case KVM_CAP_GUEST_DEBUG_HW_BPS:
r = get_num_brps();
@@ -288,7 +280,7 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
switch (vcpu->arch.target) {
default:
if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) {
- if (!cpu_has_32bit_el1())
+ if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1))
goto out;
cpu_reset = &default_regs_reset32;
} else {
--
2.26.0.110.g2183baf09c-goog
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will@kernel.org>
To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu
Cc: Mark Rutland <mark.rutland@arm.com>,
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>,
kernel-team@android.com,
Anshuman Khandual <anshuman.khandual@arm.com>,
Marc Zyngier <maz@kernel.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
linux-kernel@vger.kernel.org,
Doug Anderson <dianders@chromium.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>
Subject: [PATCH 3/8] arm64: cpufeature: Add CPU capability for AArch32 EL1 support
Date: Tue, 14 Apr 2020 22:31:09 +0100 [thread overview]
Message-ID: <20200414213114.2378-4-will@kernel.org> (raw)
In-Reply-To: <20200414213114.2378-1-will@kernel.org>
Although we emit a "SANITY CHECK" warning and taint the kernel if we
detect a CPU mismatch for AArch32 support at EL1, we still online the
CPU with disastrous consequences for any running 32-bit VMs.
Introduce a capability for AArch32 support at EL1 so that late onlining
of incompatible CPUs is forbidden.
Signed-off-by: Will Deacon <will@kernel.org>
---
arch/arm64/include/asm/cpucaps.h | 3 ++-
arch/arm64/include/asm/sysreg.h | 1 +
arch/arm64/kernel/cpufeature.c | 12 ++++++++++++
arch/arm64/kvm/reset.c | 12 ++----------
4 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
index 8eb5a088ae65..c54c674e6c21 100644
--- a/arch/arm64/include/asm/cpucaps.h
+++ b/arch/arm64/include/asm/cpucaps.h
@@ -61,7 +61,8 @@
#define ARM64_HAS_AMU_EXTN 51
#define ARM64_HAS_ADDRESS_AUTH 52
#define ARM64_HAS_GENERIC_AUTH 53
+#define ARM64_HAS_32BIT_EL1 54
-#define ARM64_NCAPS 54
+#define ARM64_NCAPS 55
#endif /* __ASM_CPUCAPS_H */
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 139cd24c181b..3d8e2f0347c4 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -653,6 +653,7 @@
#define ID_AA64PFR0_ASIMD_NI 0xf
#define ID_AA64PFR0_ASIMD_SUPPORTED 0x0
#define ID_AA64PFR0_EL1_64BIT_ONLY 0x1
+#define ID_AA64PFR0_EL1_32BIT_64BIT 0x2
#define ID_AA64PFR0_EL0_64BIT_ONLY 0x1
#define ID_AA64PFR0_EL0_32BIT_64BIT 0x2
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index b143f8bc6c52..838fe5cc8d7e 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1535,6 +1535,18 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.field_pos = ID_AA64PFR0_EL0_SHIFT,
.min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
},
+#ifdef CONFIG_KVM
+ {
+ .desc = "32-bit EL1 Support",
+ .capability = ARM64_HAS_32BIT_EL1,
+ .type = ARM64_CPUCAP_SYSTEM_FEATURE,
+ .matches = has_cpuid_feature,
+ .sys_reg = SYS_ID_AA64PFR0_EL1,
+ .sign = FTR_UNSIGNED,
+ .field_pos = ID_AA64PFR0_EL1_SHIFT,
+ .min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT,
+ },
+#endif
{
.desc = "Kernel page table isolation (KPTI)",
.capability = ARM64_UNMAP_KERNEL_AT_EL0,
diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
index 30b7ea680f66..102e5c4e01a0 100644
--- a/arch/arm64/kvm/reset.c
+++ b/arch/arm64/kvm/reset.c
@@ -46,14 +46,6 @@ static const struct kvm_regs default_regs_reset32 = {
PSR_AA32_I_BIT | PSR_AA32_F_BIT),
};
-static bool cpu_has_32bit_el1(void)
-{
- u64 pfr0;
-
- pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
- return !!(pfr0 & 0x20);
-}
-
/**
* kvm_arch_vm_ioctl_check_extension
*
@@ -66,7 +58,7 @@ int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext)
switch (ext) {
case KVM_CAP_ARM_EL1_32BIT:
- r = cpu_has_32bit_el1();
+ r = cpus_have_const_cap(ARM64_HAS_32BIT_EL1);
break;
case KVM_CAP_GUEST_DEBUG_HW_BPS:
r = get_num_brps();
@@ -288,7 +280,7 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
switch (vcpu->arch.target) {
default:
if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) {
- if (!cpu_has_32bit_el1())
+ if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1))
goto out;
cpu_reset = &default_regs_reset32;
} else {
--
2.26.0.110.g2183baf09c-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will@kernel.org>
To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu
Cc: linux-kernel@vger.kernel.org, Will Deacon <will@kernel.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Marc Zyngier <maz@kernel.org>,
Anshuman Khandual <anshuman.khandual@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>,
Doug Anderson <dianders@chromium.org>,
kernel-team@android.com
Subject: [PATCH 3/8] arm64: cpufeature: Add CPU capability for AArch32 EL1 support
Date: Tue, 14 Apr 2020 22:31:09 +0100 [thread overview]
Message-ID: <20200414213114.2378-4-will@kernel.org> (raw)
In-Reply-To: <20200414213114.2378-1-will@kernel.org>
Although we emit a "SANITY CHECK" warning and taint the kernel if we
detect a CPU mismatch for AArch32 support at EL1, we still online the
CPU with disastrous consequences for any running 32-bit VMs.
Introduce a capability for AArch32 support at EL1 so that late onlining
of incompatible CPUs is forbidden.
Signed-off-by: Will Deacon <will@kernel.org>
---
arch/arm64/include/asm/cpucaps.h | 3 ++-
arch/arm64/include/asm/sysreg.h | 1 +
arch/arm64/kernel/cpufeature.c | 12 ++++++++++++
arch/arm64/kvm/reset.c | 12 ++----------
4 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
index 8eb5a088ae65..c54c674e6c21 100644
--- a/arch/arm64/include/asm/cpucaps.h
+++ b/arch/arm64/include/asm/cpucaps.h
@@ -61,7 +61,8 @@
#define ARM64_HAS_AMU_EXTN 51
#define ARM64_HAS_ADDRESS_AUTH 52
#define ARM64_HAS_GENERIC_AUTH 53
+#define ARM64_HAS_32BIT_EL1 54
-#define ARM64_NCAPS 54
+#define ARM64_NCAPS 55
#endif /* __ASM_CPUCAPS_H */
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 139cd24c181b..3d8e2f0347c4 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -653,6 +653,7 @@
#define ID_AA64PFR0_ASIMD_NI 0xf
#define ID_AA64PFR0_ASIMD_SUPPORTED 0x0
#define ID_AA64PFR0_EL1_64BIT_ONLY 0x1
+#define ID_AA64PFR0_EL1_32BIT_64BIT 0x2
#define ID_AA64PFR0_EL0_64BIT_ONLY 0x1
#define ID_AA64PFR0_EL0_32BIT_64BIT 0x2
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index b143f8bc6c52..838fe5cc8d7e 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1535,6 +1535,18 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.field_pos = ID_AA64PFR0_EL0_SHIFT,
.min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
},
+#ifdef CONFIG_KVM
+ {
+ .desc = "32-bit EL1 Support",
+ .capability = ARM64_HAS_32BIT_EL1,
+ .type = ARM64_CPUCAP_SYSTEM_FEATURE,
+ .matches = has_cpuid_feature,
+ .sys_reg = SYS_ID_AA64PFR0_EL1,
+ .sign = FTR_UNSIGNED,
+ .field_pos = ID_AA64PFR0_EL1_SHIFT,
+ .min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT,
+ },
+#endif
{
.desc = "Kernel page table isolation (KPTI)",
.capability = ARM64_UNMAP_KERNEL_AT_EL0,
diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
index 30b7ea680f66..102e5c4e01a0 100644
--- a/arch/arm64/kvm/reset.c
+++ b/arch/arm64/kvm/reset.c
@@ -46,14 +46,6 @@ static const struct kvm_regs default_regs_reset32 = {
PSR_AA32_I_BIT | PSR_AA32_F_BIT),
};
-static bool cpu_has_32bit_el1(void)
-{
- u64 pfr0;
-
- pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
- return !!(pfr0 & 0x20);
-}
-
/**
* kvm_arch_vm_ioctl_check_extension
*
@@ -66,7 +58,7 @@ int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext)
switch (ext) {
case KVM_CAP_ARM_EL1_32BIT:
- r = cpu_has_32bit_el1();
+ r = cpus_have_const_cap(ARM64_HAS_32BIT_EL1);
break;
case KVM_CAP_GUEST_DEBUG_HW_BPS:
r = get_num_brps();
@@ -288,7 +280,7 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
switch (vcpu->arch.target) {
default:
if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) {
- if (!cpu_has_32bit_el1())
+ if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1))
goto out;
cpu_reset = &default_regs_reset32;
} else {
--
2.26.0.110.g2183baf09c-goog
next prev parent reply other threads:[~2020-04-14 21:31 UTC|newest]
Thread overview: 96+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-14 21:31 [PATCH 0/8] Relax sanity checking for mismatched AArch32 EL1 Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-14 21:31 ` [PATCH 1/8] arm64: cpufeature: Relax check for IESB support Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-15 10:02 ` Suzuki K Poulose
2020-04-15 10:02 ` Suzuki K Poulose
2020-04-15 10:02 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 2/8] arm64: cpufeature: Spell out register fields for ID_ISAR4 and ID_PFR1 Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-15 10:09 ` Suzuki K Poulose
2020-04-15 10:09 ` Suzuki K Poulose
2020-04-15 10:09 ` Suzuki K Poulose
2020-04-14 21:31 ` Will Deacon [this message]
2020-04-14 21:31 ` [PATCH 3/8] arm64: cpufeature: Add CPU capability for AArch32 EL1 support Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-15 8:55 ` Marc Zyngier
2020-04-15 8:55 ` Marc Zyngier
2020-04-15 8:55 ` Marc Zyngier
2020-04-15 17:00 ` Will Deacon
2020-04-15 17:00 ` Will Deacon
2020-04-15 17:00 ` Will Deacon
2020-04-15 10:13 ` Suzuki K Poulose
2020-04-15 10:13 ` Suzuki K Poulose
2020-04-15 10:13 ` Suzuki K Poulose
2020-04-15 10:14 ` Will Deacon
2020-04-15 10:14 ` Will Deacon
2020-04-15 10:14 ` Will Deacon
2020-04-15 13:15 ` Suzuki K Poulose
2020-04-15 13:15 ` Suzuki K Poulose
2020-04-15 13:15 ` Suzuki K Poulose
2020-04-15 13:22 ` Marc Zyngier
2020-04-15 13:22 ` Marc Zyngier
2020-04-15 13:22 ` Marc Zyngier
2020-04-17 9:44 ` Suzuki K Poulose
2020-04-17 9:44 ` Suzuki K Poulose
2020-04-17 9:44 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 4/8] arm64: cpufeature: Remove redundant call to id_aa64pfr0_32bit_el0() Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-15 10:25 ` Suzuki K Poulose
2020-04-15 10:25 ` Suzuki K Poulose
2020-04-15 10:25 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 5/8] arm64: cpufeature: Factor out checking of AArch32 features Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-15 10:36 ` Suzuki K Poulose
2020-04-15 10:36 ` Suzuki K Poulose
2020-04-15 10:36 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 6/8] arm64: cpufeature: Relax AArch32 system checks if EL1 is 64-bit only Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-15 10:43 ` Suzuki K Poulose
2020-04-15 10:43 ` Suzuki K Poulose
2020-04-15 10:43 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 7/8] arm64: cpufeature: Relax checks for AArch32 support at EL[0-2] Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-15 10:50 ` Suzuki K Poulose
2020-04-15 10:50 ` Suzuki K Poulose
2020-04-15 10:50 ` Suzuki K Poulose
2020-04-15 10:58 ` Will Deacon
2020-04-15 10:58 ` Will Deacon
2020-04-15 10:58 ` Will Deacon
2020-04-15 11:37 ` Suzuki K Poulose
2020-04-15 11:37 ` Suzuki K Poulose
2020-04-15 11:37 ` Suzuki K Poulose
2020-04-15 12:29 ` Will Deacon
2020-04-15 12:29 ` Will Deacon
2020-04-15 12:29 ` Will Deacon
2020-04-17 9:37 ` Suzuki K Poulose
2020-04-17 9:37 ` Suzuki K Poulose
2020-04-17 9:37 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 8/8] arm64: cpufeature: Add an overview comment for the cpufeature framework Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-16 11:58 ` Will Deacon
2020-04-16 11:58 ` Will Deacon
2020-04-16 11:58 ` Will Deacon
2020-04-16 14:59 ` Suzuki K Poulose
2020-04-16 14:59 ` Suzuki K Poulose
2020-04-16 14:59 ` Suzuki K Poulose
2020-04-16 15:26 ` Marc Zyngier
2020-04-16 15:26 ` Marc Zyngier
2020-04-16 15:26 ` Marc Zyngier
2020-04-16 18:12 ` Will Deacon
2020-04-16 18:12 ` Will Deacon
2020-04-16 18:12 ` Will Deacon
2020-04-16 8:39 ` [PATCH 0/8] Relax sanity checking for mismatched AArch32 EL1 Sai Prakash Ranjan
2020-04-16 8:39 ` Sai Prakash Ranjan
2020-04-16 8:39 ` Sai Prakash Ranjan
2020-04-16 10:26 ` Sai Prakash Ranjan
2020-04-16 10:26 ` Sai Prakash Ranjan
2020-04-16 10:26 ` Sai Prakash Ranjan
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