All of lore.kernel.org
 help / color / mirror / Atom feed
From: Boris Brezillon <boris.brezillon@collabora.com>
To: "Ramuthevar,Vadivel MuruganX" 
	<vadivel.muruganx.ramuthevar@linux.intel.com>
Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org,
	devicetree@vger.kernel.org, miquel.raynal@bootlin.com,
	richard@nod.at, vigneshr@ti.com, arnd@arndb.de,
	brendanhiggins@google.com, tglx@linutronix.de,
	anders.roxell@linaro.org, masonccyang@mxic.com.tw,
	piotrs@cadence.com, robh+dt@kernel.org,
	linux-mips@vger.kernel.org, hauke.mehrtens@intel.com,
	andriy.shevchenko@intel.com, qi-ming.wu@intel.com,
	cheol.yong.kim@intel.com
Subject: Re: [PATCH v2 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC
Date: Mon, 20 Apr 2020 10:29:59 +0200	[thread overview]
Message-ID: <20200420102959.2659774d@collabora.com> (raw)
In-Reply-To: <20200417082147.43384-3-vadivel.muruganx.ramuthevar@linux.intel.com>

On Fri, 17 Apr 2020 16:21:47 +0800
"Ramuthevar,Vadivel MuruganX"
<vadivel.muruganx.ramuthevar@linux.intel.com> wrote:

> +
> +	res = devm_platform_ioremap_resource_byname(pdev, lgm_host->cs_name);
> +	lgm_host->nandaddr_va = res;
> +	nandaddr_pa = res->start;
> +	if (IS_ERR(lgm_host->nandaddr_va))
> +		return PTR_ERR(lgm_host->nandaddr_va);

Hm, I didn't realize you needed the physical address for DMA transfers.
Just use platform_get_resource_by_name()+devm_ioremap_resource() in
that case.


> +
> +	writel(LGM_BUSCON_CMULT_V4 | LGM_BUSCON_RECOVC(1) |
> +	       LGM_BUSCON_HOLDC(1) | LGM_BUSCON_WAITRDC(2) |
> +	       LGM_BUSCON_WAITWRC(2) | LGM_BUSCON_BCGEN_CS | LGM_BUSCON_ALEC |
> +	       LGM_BUSCON_SETUP_EN, lgm_host->lgm_va + LGM_BUSCON(cs));

I'm sure some the timings you hardcode here can be extracted from the
NAND timings. Can you see if you can implement ->setup_data_interface()
instead.

WARNING: multiple messages have this Message-ID (diff)
From: Boris Brezillon <boris.brezillon@collabora.com>
To: "Ramuthevar,Vadivel MuruganX"
	<vadivel.muruganx.ramuthevar@linux.intel.com>
Cc: cheol.yong.kim@intel.com, devicetree@vger.kernel.org,
	andriy.shevchenko@intel.com, anders.roxell@linaro.org,
	vigneshr@ti.com, arnd@arndb.de, hauke.mehrtens@intel.com,
	richard@nod.at, qi-ming.wu@intel.com, brendanhiggins@google.com,
	linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org,
	robh+dt@kernel.org, linux-mtd@lists.infradead.org,
	miquel.raynal@bootlin.com, tglx@linutronix.de,
	masonccyang@mxic.com.tw, piotrs@cadence.com
Subject: Re: [PATCH v2 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC
Date: Mon, 20 Apr 2020 10:29:59 +0200	[thread overview]
Message-ID: <20200420102959.2659774d@collabora.com> (raw)
In-Reply-To: <20200417082147.43384-3-vadivel.muruganx.ramuthevar@linux.intel.com>

On Fri, 17 Apr 2020 16:21:47 +0800
"Ramuthevar,Vadivel MuruganX"
<vadivel.muruganx.ramuthevar@linux.intel.com> wrote:

> +
> +	res = devm_platform_ioremap_resource_byname(pdev, lgm_host->cs_name);
> +	lgm_host->nandaddr_va = res;
> +	nandaddr_pa = res->start;
> +	if (IS_ERR(lgm_host->nandaddr_va))
> +		return PTR_ERR(lgm_host->nandaddr_va);

Hm, I didn't realize you needed the physical address for DMA transfers.
Just use platform_get_resource_by_name()+devm_ioremap_resource() in
that case.


> +
> +	writel(LGM_BUSCON_CMULT_V4 | LGM_BUSCON_RECOVC(1) |
> +	       LGM_BUSCON_HOLDC(1) | LGM_BUSCON_WAITRDC(2) |
> +	       LGM_BUSCON_WAITWRC(2) | LGM_BUSCON_BCGEN_CS | LGM_BUSCON_ALEC |
> +	       LGM_BUSCON_SETUP_EN, lgm_host->lgm_va + LGM_BUSCON(cs));

I'm sure some the timings you hardcode here can be extracted from the
NAND timings. Can you see if you can implement ->setup_data_interface()
instead.

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

  parent reply	other threads:[~2020-04-20  8:30 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-17  8:21 [PATCH v2 0/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC Ramuthevar,Vadivel MuruganX
2020-04-17  8:21 ` Ramuthevar, Vadivel MuruganX
2020-04-17  8:21 ` [PATCH v2 1/2] dt-bindings: mtd: Add YAML for Nand Flash Controller support Ramuthevar,Vadivel MuruganX
2020-04-17  8:21   ` Ramuthevar, Vadivel MuruganX
2020-04-17  8:21 ` [PATCH v2 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC Ramuthevar,Vadivel MuruganX
2020-04-17  8:21   ` Ramuthevar, Vadivel MuruganX
2020-04-17 17:05   ` Hauke Mehrtens
2020-04-17 17:05     ` Hauke Mehrtens
2020-04-20  3:49     ` Ramuthevar, Vadivel MuruganX
2020-04-20  3:49       ` Ramuthevar, Vadivel MuruganX
2020-04-18  8:55   ` Boris Brezillon
2020-04-18  8:55     ` Boris Brezillon
2020-04-19 22:20     ` Andy Shevchenko
2020-04-19 22:20       ` Andy Shevchenko
2020-04-20  9:17       ` Boris Brezillon
2020-04-20  9:17         ` Boris Brezillon
2020-04-20  9:44         ` Andy Shevchenko
2020-04-20  9:44           ` Andy Shevchenko
2020-04-20  9:52           ` Boris Brezillon
2020-04-20  9:52             ` Boris Brezillon
2020-04-20 10:14             ` Andy Shevchenko
2020-04-20 10:14               ` Andy Shevchenko
2020-04-20 10:28               ` Boris Brezillon
2020-04-20 10:28                 ` Boris Brezillon
2020-04-20 10:41                 ` Andy Shevchenko
2020-04-20 10:41                   ` Andy Shevchenko
2020-04-20 11:06                   ` Boris Brezillon
2020-04-20 11:06                     ` Boris Brezillon
2020-04-20  4:18     ` Ramuthevar, Vadivel MuruganX
2020-04-20  4:18       ` Ramuthevar, Vadivel MuruganX
2020-04-20  7:40       ` Boris Brezillon
2020-04-20  7:40         ` Boris Brezillon
2020-04-20  8:51         ` Ramuthevar, Vadivel MuruganX
2020-04-20  8:51           ` Ramuthevar, Vadivel MuruganX
2020-04-27 15:38     ` Miquel Raynal
2020-04-27 15:38       ` Miquel Raynal
2020-04-27 18:30       ` Boris Brezillon
2020-04-27 18:30         ` Boris Brezillon
2020-04-19 22:28   ` Andy Shevchenko
2020-04-19 22:28     ` Andy Shevchenko
2020-04-20  3:28     ` Ramuthevar, Vadivel MuruganX
2020-04-20  3:28       ` Ramuthevar, Vadivel MuruganX
2020-04-20  8:29   ` Boris Brezillon [this message]
2020-04-20  8:29     ` Boris Brezillon
2020-04-20  9:15     ` Ramuthevar, Vadivel MuruganX
2020-04-20  9:15       ` Ramuthevar, Vadivel MuruganX

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200420102959.2659774d@collabora.com \
    --to=boris.brezillon@collabora.com \
    --cc=anders.roxell@linaro.org \
    --cc=andriy.shevchenko@intel.com \
    --cc=arnd@arndb.de \
    --cc=brendanhiggins@google.com \
    --cc=cheol.yong.kim@intel.com \
    --cc=devicetree@vger.kernel.org \
    --cc=hauke.mehrtens@intel.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mips@vger.kernel.org \
    --cc=linux-mtd@lists.infradead.org \
    --cc=masonccyang@mxic.com.tw \
    --cc=miquel.raynal@bootlin.com \
    --cc=piotrs@cadence.com \
    --cc=qi-ming.wu@intel.com \
    --cc=richard@nod.at \
    --cc=robh+dt@kernel.org \
    --cc=tglx@linutronix.de \
    --cc=vadivel.muruganx.ramuthevar@linux.intel.com \
    --cc=vigneshr@ti.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.