Re: [Intel-gfx] [CI 2/2] drm/i915/gt: Use the RPM config register to determine clk frequencies

[kbuild test robot <lkp@intel.com>]

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Hi Chris,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on next-20200422]
[cannot apply to drm-intel/for-linux-next drm-tip/drm-tip v5.7-rc2 v5.7-rc1 v5.6 v5.7-rc2]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-gt-Trace-RPS-events/20200423-050247
base:    a5840f9618a90ecbe1617f7632482563c0ee307e
config: i386-allyesconfig (attached as .config)
compiler: gcc-7 (Ubuntu 7.5.0-6ubuntu2) 7.5.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:82,
                    from drivers/gpu/drm/i915/gt/intel_rps.c:9:
   drivers/gpu/drm/i915/gt/intel_rps.c: In function 'gen9_rps_enable':
>> drivers/gpu/drm/i915/gt/intel_rps.c:951:10: error: implicit declaration of function 'GT_INTERVAL_FROM_US'; did you mean 'NTP_INTERVAL_FREQ'? [-Werror=implicit-function-declaration]
             GT_INTERVAL_FROM_US(i915, 1000000));
             ^
   drivers/gpu/drm/i915/intel_uncore.h:378:57: note: in definition of macro 'intel_uncore_write_fw'
    #define intel_uncore_write_fw(...) __raw_uncore_write32(__VA_ARGS__)
                                                            ^~~~~~~~~~~
>> drivers/gpu/drm/i915/gt/intel_rps.c:951:30: error: 'i915' undeclared (first use in this function); did you mean 'to_i915'?
             GT_INTERVAL_FROM_US(i915, 1000000));
                                 ^
   drivers/gpu/drm/i915/intel_uncore.h:378:57: note: in definition of macro 'intel_uncore_write_fw'
    #define intel_uncore_write_fw(...) __raw_uncore_write32(__VA_ARGS__)
                                                            ^~~~~~~~~~~
   drivers/gpu/drm/i915/gt/intel_rps.c:951:30: note: each undeclared identifier is reported only once for each function it appears in
             GT_INTERVAL_FROM_US(i915, 1000000));
                                 ^
   drivers/gpu/drm/i915/intel_uncore.h:378:57: note: in definition of macro 'intel_uncore_write_fw'
    #define intel_uncore_write_fw(...) __raw_uncore_write32(__VA_ARGS__)
                                                            ^~~~~~~~~~~
   cc1: some warnings being treated as errors

vim +951 drivers/gpu/drm/i915/gt/intel_rps.c

3e7abf8141935d Andi Shyti   2019-10-24  937  
3e7abf8141935d Andi Shyti   2019-10-24  938  /* See the Gen9_GT_PM_Programming_Guide doc for the below */
3e7abf8141935d Andi Shyti   2019-10-24  939  static bool gen9_rps_enable(struct intel_rps *rps)
3e7abf8141935d Andi Shyti   2019-10-24  940  {
ba8c1ce62dadbf Chris Wilson 2020-04-21  941  	struct intel_gt *gt = rps_to_gt(rps);
ba8c1ce62dadbf Chris Wilson 2020-04-21  942  	struct intel_uncore *uncore = gt->uncore;
3e7abf8141935d Andi Shyti   2019-10-24  943  
3e7abf8141935d Andi Shyti   2019-10-24  944  	/* Program defaults and thresholds for RPS */
ba8c1ce62dadbf Chris Wilson 2020-04-21  945  	if (IS_GEN(gt->i915, 9))
3e7abf8141935d Andi Shyti   2019-10-24  946  		intel_uncore_write_fw(uncore, GEN6_RC_VIDEO_FREQ,
3e7abf8141935d Andi Shyti   2019-10-24  947  				      GEN9_FREQUENCY(rps->rp1_freq));
3e7abf8141935d Andi Shyti   2019-10-24  948  
3e7abf8141935d Andi Shyti   2019-10-24  949  	/* 1 second timeout */
3e7abf8141935d Andi Shyti   2019-10-24  950  	intel_uncore_write_fw(uncore, GEN6_RP_DOWN_TIMEOUT,
3e7abf8141935d Andi Shyti   2019-10-24 @951  			      GT_INTERVAL_FROM_US(i915, 1000000));
3e7abf8141935d Andi Shyti   2019-10-24  952  
3e7abf8141935d Andi Shyti   2019-10-24  953  	intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 0xa);
3e7abf8141935d Andi Shyti   2019-10-24  954  
3e7abf8141935d Andi Shyti   2019-10-24  955  	return rps_reset(rps);
3e7abf8141935d Andi Shyti   2019-10-24  956  }
3e7abf8141935d Andi Shyti   2019-10-24  957  

:::::: The code at line 951 was first introduced by commit
:::::: 3e7abf8141935ded77abeb622480bf4a14241ece drm/i915: Extract GT render power state management

:::::: TO: Andi Shyti <andi@etezian.org>
:::::: CC: Chris Wilson <chris@chris-wilson.co.uk>

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

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