From: Boris Brezillon <boris.brezillon@collabora.com>
To: "Ramuthevar,
Vadivel MuruganX" <vadivel.muruganx.ramuthevar@linux.intel.com>
Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org,
devicetree@vger.kernel.org, cheol.yong.kim@intel.com,
hauke.mehrtens@intel.com, qi-ming.wu@intel.com,
anders.roxell@linaro.org, vigneshr@ti.com, arnd@arndb.de,
richard@nod.at, brendanhiggins@google.com,
linux-mips@vger.kernel.org, robh+dt@kernel.org,
miquel.raynal@bootlin.com, tglx@linutronix.de,
masonccyang@mxic.com.tw, andriy.shevchenko@intel.com
Subject: Re: [PATCH v4 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC
Date: Wed, 29 Apr 2020 16:22:49 +0200 [thread overview]
Message-ID: <20200429162249.55d38ee8@collabora.com> (raw)
In-Reply-To: <20200429104205.18780-3-vadivel.muruganx.ramuthevar@linux.intel.com>
On Wed, 29 Apr 2020 18:42:05 +0800
"Ramuthevar, Vadivel MuruganX"
<vadivel.muruganx.ramuthevar@linux.intel.com> wrote:
> +
> +#define EBU_ADDR_SEL(n) (0x20 + (n) * 4)
> +#define EBU_ADDR_MASK (5 << 4)
It's still unclear what ADDR_MASK is for. Can you add a comment
explaining what it does?
> +#define EBU_ADDR_SEL_REGEN 0x1
> +
> + writel(lower_32_bits(ebu_host->cs[ebu_host->cs_num].nand_pa) |
> + EBU_ADDR_SEL_REGEN | EBU_ADDR_MASK,
> + ebu_host->ebu + EBU_ADDR_SEL(reg));
> +
> + writel(EBU_MEM_BASE_CS_0 | EBU_ADDR_MASK | EBU_ADDR_SEL_REGEN,
> + ebu_host->ebu + EBU_ADDR_SEL(0));
> + writel(EBU_MEM_BASE_CS_1 | EBU_ADDR_MASK | EBU_ADDR_SEL_REGEN,
> + ebu_host->ebu + EBU_ADDR_SEL(reg));
That's super weird. You seem to set EBU_ADDR_SEL(reg) twice. Are you
sure that's needed, and are we setting EBU_ADDR_SEL(0) here?
WARNING: multiple messages have this Message-ID (diff)
From: Boris Brezillon <boris.brezillon@collabora.com>
To: "Ramuthevar,
Vadivel MuruganX" <vadivel.muruganx.ramuthevar@linux.intel.com>
Cc: cheol.yong.kim@intel.com, devicetree@vger.kernel.org,
masonccyang@mxic.com.tw, anders.roxell@linaro.org,
vigneshr@ti.com, arnd@arndb.de, hauke.mehrtens@intel.com,
richard@nod.at, brendanhiggins@google.com,
linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org,
robh+dt@kernel.org, linux-mtd@lists.infradead.org,
miquel.raynal@bootlin.com, tglx@linutronix.de,
qi-ming.wu@intel.com, andriy.shevchenko@intel.com
Subject: Re: [PATCH v4 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC
Date: Wed, 29 Apr 2020 16:22:49 +0200 [thread overview]
Message-ID: <20200429162249.55d38ee8@collabora.com> (raw)
In-Reply-To: <20200429104205.18780-3-vadivel.muruganx.ramuthevar@linux.intel.com>
On Wed, 29 Apr 2020 18:42:05 +0800
"Ramuthevar, Vadivel MuruganX"
<vadivel.muruganx.ramuthevar@linux.intel.com> wrote:
> +
> +#define EBU_ADDR_SEL(n) (0x20 + (n) * 4)
> +#define EBU_ADDR_MASK (5 << 4)
It's still unclear what ADDR_MASK is for. Can you add a comment
explaining what it does?
> +#define EBU_ADDR_SEL_REGEN 0x1
> +
> + writel(lower_32_bits(ebu_host->cs[ebu_host->cs_num].nand_pa) |
> + EBU_ADDR_SEL_REGEN | EBU_ADDR_MASK,
> + ebu_host->ebu + EBU_ADDR_SEL(reg));
> +
> + writel(EBU_MEM_BASE_CS_0 | EBU_ADDR_MASK | EBU_ADDR_SEL_REGEN,
> + ebu_host->ebu + EBU_ADDR_SEL(0));
> + writel(EBU_MEM_BASE_CS_1 | EBU_ADDR_MASK | EBU_ADDR_SEL_REGEN,
> + ebu_host->ebu + EBU_ADDR_SEL(reg));
That's super weird. You seem to set EBU_ADDR_SEL(reg) twice. Are you
sure that's needed, and are we setting EBU_ADDR_SEL(0) here?
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next prev parent reply other threads:[~2020-04-29 14:22 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-29 10:42 [PATCH v4 0/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC Ramuthevar,Vadivel MuruganX
2020-04-29 10:42 ` Ramuthevar, Vadivel MuruganX
2020-04-29 10:42 ` [PATCH v4 1/2] dt-bindings: mtd: Add YAML for Nand Flash Controller support Ramuthevar,Vadivel MuruganX
2020-04-29 10:42 ` Ramuthevar, Vadivel MuruganX
2020-04-29 15:34 ` Boris Brezillon
2020-04-29 15:34 ` Boris Brezillon
2020-04-30 1:07 ` Ramuthevar, Vadivel MuruganX
2020-04-30 1:07 ` Ramuthevar, Vadivel MuruganX
2020-04-29 10:42 ` [PATCH v4 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC Ramuthevar,Vadivel MuruganX
2020-04-29 10:42 ` Ramuthevar, Vadivel MuruganX
2020-04-29 11:33 ` Boris Brezillon
2020-04-29 11:33 ` Boris Brezillon
2020-04-29 13:29 ` Ramuthevar, Vadivel MuruganX
2020-04-29 13:29 ` Ramuthevar, Vadivel MuruganX
2020-04-29 13:32 ` Boris Brezillon
2020-04-29 13:32 ` Boris Brezillon
2020-04-29 14:26 ` Ramuthevar, Vadivel MuruganX
2020-04-29 14:26 ` Ramuthevar, Vadivel MuruganX
2020-04-29 14:22 ` Boris Brezillon [this message]
2020-04-29 14:22 ` Boris Brezillon
2020-04-29 14:33 ` Ramuthevar, Vadivel MuruganX
2020-04-29 14:33 ` Ramuthevar, Vadivel MuruganX
2020-04-29 14:48 ` Boris Brezillon
2020-04-29 14:48 ` Boris Brezillon
2020-04-29 15:18 ` Ramuthevar, Vadivel MuruganX
2020-04-29 15:18 ` Ramuthevar, Vadivel MuruganX
2020-04-29 15:29 ` Ramuthevar, Vadivel MuruganX
2020-04-29 15:29 ` Ramuthevar, Vadivel MuruganX
2020-04-29 15:31 ` Boris Brezillon
2020-04-29 15:31 ` Boris Brezillon
2020-04-30 7:50 ` Ramuthevar, Vadivel MuruganX
2020-04-30 7:50 ` Ramuthevar, Vadivel MuruganX
2020-04-30 8:21 ` Boris Brezillon
2020-04-30 8:21 ` Boris Brezillon
2020-04-30 8:30 ` Ramuthevar, Vadivel MuruganX
2020-04-30 8:30 ` Ramuthevar, Vadivel MuruganX
2020-04-30 8:36 ` Boris Brezillon
2020-04-30 8:36 ` Boris Brezillon
2020-04-30 9:07 ` Ramuthevar, Vadivel MuruganX
2020-04-30 9:07 ` Ramuthevar, Vadivel MuruganX
2020-04-30 12:36 ` Boris Brezillon
2020-04-30 12:36 ` Boris Brezillon
2020-04-30 13:01 ` Boris Brezillon
2020-04-30 13:01 ` Boris Brezillon
2020-05-04 1:58 ` Ramuthevar, Vadivel MuruganX
2020-05-04 1:58 ` Ramuthevar, Vadivel MuruganX
2020-05-04 2:02 ` Ramuthevar, Vadivel MuruganX
2020-05-04 2:02 ` Ramuthevar, Vadivel MuruganX
2020-05-04 7:08 ` Boris Brezillon
2020-05-04 7:08 ` Boris Brezillon
2020-05-04 7:15 ` Ramuthevar, Vadivel MuruganX
2020-05-04 7:15 ` Ramuthevar, Vadivel MuruganX
2020-05-04 7:17 ` Boris Brezillon
2020-05-04 7:17 ` Boris Brezillon
2020-05-04 8:50 ` Ramuthevar, Vadivel MuruganX
2020-05-04 8:50 ` Ramuthevar, Vadivel MuruganX
2020-05-04 8:58 ` Boris Brezillon
2020-05-04 8:58 ` Boris Brezillon
2020-05-04 9:17 ` Ramuthevar, Vadivel MuruganX
2020-05-04 9:17 ` Ramuthevar, Vadivel MuruganX
2020-05-05 5:28 ` Ramuthevar, Vadivel MuruganX
2020-05-05 5:28 ` Ramuthevar, Vadivel MuruganX
2020-05-05 7:00 ` Boris Brezillon
2020-05-05 7:00 ` Boris Brezillon
2020-05-05 7:17 ` Ramuthevar, Vadivel MuruganX
2020-05-05 7:17 ` Ramuthevar, Vadivel MuruganX
2020-05-04 1:54 ` Ramuthevar, Vadivel MuruganX
2020-05-04 1:54 ` Ramuthevar, Vadivel MuruganX
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