Re: [PATCH V2] MIPS: perf: Add hardware perf events support for new Loongson-3

[Thomas Bogendoerfer <tsbogend@alpha.franken.de>]

On Thu, Apr 30, 2020 at 03:30:55PM +0800, Huacai Chen wrote:
> Hi, Thomas,
> 
> On Thu, Apr 30, 2020 at 2:33 AM Thomas Bogendoerfer
> <tsbogend@alpha.franken.de> wrote:
> >
> > On Wed, Apr 29, 2020 at 03:26:10PM +0800, Huacai Chen wrote:
> > > New Loongson-3 means Loongson-3A R2 (Loongson-3A2000) and newer CPUs.
> > > Loongson-3 processors have three types of PMU types (so there are three
> > > event maps): Loongson-3A1000/Loonngson-3B1000/Loongson-3B1500 is Type-1,
> > > Loongson-3A2000/Loongson-3A3000 is Type-2, Loongson-3A4000+ is Type-3.
> > >
> > > Signed-off-by: Huacai Chen <chenhc@lemote.com>
> > > ---
> > >  .../asm/mach-loongson64/cpu-feature-overrides.h    |   1 +
> > >  arch/mips/kernel/perf_event_mipsxx.c               | 358 +++++++++++++++++++--
> >
> > checkpatch warns about missing break/fallthrough statement and indention
> > problems, could please look at this ? And as all the new code is only
> > usefull for loongsoon CPUs could you try to only compile it in, if it's
> > enabled for the image ?
> OK, I will solve the "fallthrough" warnings and indention warnings.
> But the other problem is I should use #ifdef CONFIG_CPU_LOONGSON64 to
> guard all new code in this file? I remember that Paul Burton suggest
> us to avoid use #ifdef and use runtime detection instead.

if you do the cpu checks for current_cpu_type() == CPU_LOONGSON64
the compiler will eliminate not needed cpu code. Looks like most
of the new code is done inside case CPU_LOONGSON64 blocks, so
that is fine. Could you check how much size increase you get for
a non loongson64 target with your patch ?


Thomas.

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