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From: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Jonathan Hunter
	<jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
	Nicolas Chauvet <kwizart-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	Russell King <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org>,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: Re: [PATCH v1] ARM: tegra: Correct PL310 Auxiliary Control Register initialization
Date: Wed, 6 May 2020 18:44:56 +0200	[thread overview]
Message-ID: <20200506164456.GC2723987@ulmo> (raw)
In-Reply-To: <20200313090104.20750-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

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On Fri, Mar 13, 2020 at 12:01:04PM +0300, Dmitry Osipenko wrote:
> The PL310 Auxiliary Control Register shouldn't have the "Full line of
> zero" optimization bit being set before L2 cache is enabled. The L2X0
> driver takes care of enabling the optimization by itself.
> 
> This patch fixes a noisy error message on Tegra20 and Tegra30 telling
> that cache optimization is erroneously enabled without enabling it for
> the CPU:
> 
> 	L2C-310: enabling full line of zeros but not enabled in Cortex-A9
> 
> Cc: <stable-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
> Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  arch/arm/mach-tegra/tegra.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Applied to for-5.8/arm/core, thanks.

Thierry

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WARNING: multiple messages have this Message-ID (diff)
From: Thierry Reding <thierry.reding@gmail.com>
To: Dmitry Osipenko <digetx@gmail.com>
Cc: Nicolas Chauvet <kwizart@gmail.com>,
	linux-tegra@vger.kernel.org, Russell King <linux@armlinux.org.uk>,
	linux-arm-kernel@lists.infradead.org,
	Jonathan Hunter <jonathanh@nvidia.com>
Subject: Re: [PATCH v1] ARM: tegra: Correct PL310 Auxiliary Control Register initialization
Date: Wed, 6 May 2020 18:44:56 +0200	[thread overview]
Message-ID: <20200506164456.GC2723987@ulmo> (raw)
In-Reply-To: <20200313090104.20750-1-digetx@gmail.com>


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On Fri, Mar 13, 2020 at 12:01:04PM +0300, Dmitry Osipenko wrote:
> The PL310 Auxiliary Control Register shouldn't have the "Full line of
> zero" optimization bit being set before L2 cache is enabled. The L2X0
> driver takes care of enabling the optimization by itself.
> 
> This patch fixes a noisy error message on Tegra20 and Tegra30 telling
> that cache optimization is erroneously enabled without enabling it for
> the CPU:
> 
> 	L2C-310: enabling full line of zeros but not enabled in Cortex-A9
> 
> Cc: <stable@vger.kernel.org>
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> ---
>  arch/arm/mach-tegra/tegra.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Applied to for-5.8/arm/core, thanks.

Thierry

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  parent reply	other threads:[~2020-05-06 16:44 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-13  9:01 [PATCH v1] ARM: tegra: Correct PL310 Auxiliary Control Register initialization Dmitry Osipenko
2020-03-13  9:01 ` Dmitry Osipenko
     [not found] ` <20200313090104.20750-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-03-13 10:05   ` Nicolas Chauvet
2020-03-13 10:05     ` Nicolas Chauvet
2020-05-06 16:44   ` Thierry Reding [this message]
2020-05-06 16:44     ` Thierry Reding

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