From: Rob Herring <robh@kernel.org>
To: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org, linux-usb@vger.kernel.org,
linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Mark Brown <broonie@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org
Subject: [PATCH 1/5] spi: dt-bindings: sifive: Add missing 2nd register region
Date: Tue, 12 May 2020 15:45:39 -0500 [thread overview]
Message-ID: <20200512204543.22090-1-robh@kernel.org> (raw)
The 'reg' description and example have a 2nd register region for memory
mapped flash, but the schema says there is only 1 region. Fix this.
Cc: Mark Brown <broonie@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: linux-spi@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
Please ack, dependency for patch 5.
Documentation/devicetree/bindings/spi/spi-sifive.yaml | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/spi-sifive.yaml b/Documentation/devicetree/bindings/spi/spi-sifive.yaml
index 28040598bfae..fb583e57c1f2 100644
--- a/Documentation/devicetree/bindings/spi/spi-sifive.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-sifive.yaml
@@ -32,11 +32,10 @@ properties:
https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi
reg:
- maxItems: 1
-
- description:
- Physical base address and size of SPI registers map
- A second (optional) range can indicate memory mapped flash
+ minItems: 1
+ items:
+ - description: SPI registers region
+ - description: Memory mapped flash region
interrupts:
maxItems: 1
--
2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: devicetree@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-spi@vger.kernel.org, Mark Brown <broonie@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org
Subject: [PATCH 1/5] spi: dt-bindings: sifive: Add missing 2nd register region
Date: Tue, 12 May 2020 15:45:39 -0500 [thread overview]
Message-ID: <20200512204543.22090-1-robh@kernel.org> (raw)
The 'reg' description and example have a 2nd register region for memory
mapped flash, but the schema says there is only 1 region. Fix this.
Cc: Mark Brown <broonie@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: linux-spi@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
Please ack, dependency for patch 5.
Documentation/devicetree/bindings/spi/spi-sifive.yaml | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/spi-sifive.yaml b/Documentation/devicetree/bindings/spi/spi-sifive.yaml
index 28040598bfae..fb583e57c1f2 100644
--- a/Documentation/devicetree/bindings/spi/spi-sifive.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-sifive.yaml
@@ -32,11 +32,10 @@ properties:
https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi
reg:
- maxItems: 1
-
- description:
- Physical base address and size of SPI registers map
- A second (optional) range can indicate memory mapped flash
+ minItems: 1
+ items:
+ - description: SPI registers region
+ - description: Memory mapped flash region
interrupts:
maxItems: 1
--
2.20.1
next reply other threads:[~2020-05-12 20:46 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-12 20:45 Rob Herring [this message]
2020-05-12 20:45 ` [PATCH 1/5] spi: dt-bindings: sifive: Add missing 2nd register region Rob Herring
2020-05-12 20:45 ` [PATCH 2/5] dt-bindings: usb: ehci: " Rob Herring
2020-05-13 12:05 ` Greg Kroah-Hartman
2020-05-12 20:45 ` [PATCH 3/5] dt-bindings: ufs: ti: Fix address properties handling Rob Herring
2020-05-13 7:49 ` Vignesh Raghavendra
2020-05-12 20:45 ` [PATCH 4/5] dt-bindings: ufs: ti: Add missing 'additionalProperties: false' Rob Herring
2020-05-13 7:49 ` Vignesh Raghavendra
2020-05-12 20:45 ` [PATCH 5/5] dt-bindings: Fix incorrect 'reg' property sizes Rob Herring
2020-05-12 21:46 ` Stephen Boyd
2020-05-13 7:04 ` Geert Uytterhoeven
2020-05-13 12:10 ` [PATCH 1/5] spi: dt-bindings: sifive: Add missing 2nd register region Mark Brown
2020-05-13 12:10 ` Mark Brown
2020-05-13 13:02 ` Rob Herring
2020-05-13 13:02 ` Rob Herring
2020-05-13 14:03 ` Mark Brown
2020-05-13 14:03 ` Mark Brown
2020-05-13 21:22 ` Paul Walmsley
2020-05-13 21:22 ` Paul Walmsley
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