From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: Venkateshwar Rao Gannavarapu <VGANNAVA@xilinx.com>
Cc: Sandip Kothari <sandipk@xilinx.com>,
"airlied@linux.ie" <airlied@linux.ie>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"dri-devel@lists.freedesktop.org"
<dri-devel@lists.freedesktop.org>
Subject: Re: [RFC PATCH 2/2] drm: xlnx: driver for Xilinx DSI TX Subsystem
Date: Sun, 7 Jun 2020 05:25:18 +0300 [thread overview]
Message-ID: <20200607022518.GA7339@pendragon.ideasonboard.com> (raw)
In-Reply-To: <CY4PR02MB2790B791578160F257049FEAB18D0@CY4PR02MB2790.namprd02.prod.outlook.com>
Hi GVRao,
On Sun, May 31, 2020 at 05:41:50PM +0000, Venkateshwar Rao Gannavarapu wrote:
> On Sunday, May 24, 2020 8:38 AM, Laurent Pinchart wrote:
> > On Mon, May 04, 2020 at 11:43:48AM -0700, Hyun Kwon wrote:
> >> On Mon, 2020-04-20 at 14:20:56 -0700, Venkateshwar Rao Gannavarapu wrote:
> >>> The Xilinx MIPI DSI Tx Subsystem soft IP is used to display video
> >>> data from AXI-4 stream interface.
> >>>
> >>> It supports upto 4 lanes, optional register interface for the DPHY,
> >>
> >> I don't see the register interface for dphy support.
> >
> > I think the D-PHY should be supported through a PHY driver, as it seems to be
> > shared between different subsystems.
>
> IP has the provision to read DPHY register for debug purpose only.
> No programming of DPHY is required in subsystem.
Do you know if this is the same D-PHY as used in the CSI2-RX subsystem ?
> >>> multiple RGB color formats, command mode and video mode.
> >>> This is a MIPI-DSI host driver and provides DSI bus for panels.
> >>> This driver also helps to communicate with its panel using panel
> >>> framework.
> >>>
> >>> Signed-off-by: Venkateshwar Rao Gannavarapu <venkateshwar.rao.gannavarapu@xilinx.com>
> >>> ---
> >>> drivers/gpu/drm/xlnx/Kconfig | 11 +
> >>> drivers/gpu/drm/xlnx/Makefile | 2 +
> >>> drivers/gpu/drm/xlnx/xlnx_dsi.c | 755 ++++++++++++++++++++++++++++++++++++++++
> >
> > Daniel Vetter has recently expressed his opiion that bridge drivers should go to
> > drivers/gpu/drm/bridge/. It would then be drivers/gpu/drm/bridge/xlnx/. I don't
> > have a strong opinion myself.
> >
> >>> 3 files changed, 768 insertions(+)
> >>> create mode 100644 drivers/gpu/drm/xlnx/xlnx_dsi.c
[snip]
--
Regards,
Laurent Pinchart
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dri-devel@lists.freedesktop.org
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WARNING: multiple messages have this Message-ID (diff)
From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: Venkateshwar Rao Gannavarapu <VGANNAVA@xilinx.com>
Cc: Hyun Kwon <hyunk@xilinx.com>,
"dri-devel@lists.freedesktop.org"
<dri-devel@lists.freedesktop.org>,
"airlied@linux.ie" <airlied@linux.ie>,
"daniel@ffwll.ch" <daniel@ffwll.ch>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Sandip Kothari <sandipk@xilinx.com>
Subject: Re: [RFC PATCH 2/2] drm: xlnx: driver for Xilinx DSI TX Subsystem
Date: Sun, 7 Jun 2020 05:25:18 +0300 [thread overview]
Message-ID: <20200607022518.GA7339@pendragon.ideasonboard.com> (raw)
In-Reply-To: <CY4PR02MB2790B791578160F257049FEAB18D0@CY4PR02MB2790.namprd02.prod.outlook.com>
Hi GVRao,
On Sun, May 31, 2020 at 05:41:50PM +0000, Venkateshwar Rao Gannavarapu wrote:
> On Sunday, May 24, 2020 8:38 AM, Laurent Pinchart wrote:
> > On Mon, May 04, 2020 at 11:43:48AM -0700, Hyun Kwon wrote:
> >> On Mon, 2020-04-20 at 14:20:56 -0700, Venkateshwar Rao Gannavarapu wrote:
> >>> The Xilinx MIPI DSI Tx Subsystem soft IP is used to display video
> >>> data from AXI-4 stream interface.
> >>>
> >>> It supports upto 4 lanes, optional register interface for the DPHY,
> >>
> >> I don't see the register interface for dphy support.
> >
> > I think the D-PHY should be supported through a PHY driver, as it seems to be
> > shared between different subsystems.
>
> IP has the provision to read DPHY register for debug purpose only.
> No programming of DPHY is required in subsystem.
Do you know if this is the same D-PHY as used in the CSI2-RX subsystem ?
> >>> multiple RGB color formats, command mode and video mode.
> >>> This is a MIPI-DSI host driver and provides DSI bus for panels.
> >>> This driver also helps to communicate with its panel using panel
> >>> framework.
> >>>
> >>> Signed-off-by: Venkateshwar Rao Gannavarapu <venkateshwar.rao.gannavarapu@xilinx.com>
> >>> ---
> >>> drivers/gpu/drm/xlnx/Kconfig | 11 +
> >>> drivers/gpu/drm/xlnx/Makefile | 2 +
> >>> drivers/gpu/drm/xlnx/xlnx_dsi.c | 755 ++++++++++++++++++++++++++++++++++++++++
> >
> > Daniel Vetter has recently expressed his opiion that bridge drivers should go to
> > drivers/gpu/drm/bridge/. It would then be drivers/gpu/drm/bridge/xlnx/. I don't
> > have a strong opinion myself.
> >
> >>> 3 files changed, 768 insertions(+)
> >>> create mode 100644 drivers/gpu/drm/xlnx/xlnx_dsi.c
[snip]
--
Regards,
Laurent Pinchart
next prev parent reply other threads:[~2020-06-07 2:25 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-20 21:20 [RFC PATCH 0/2] Add Xilinx DSI-TX DRM driver Venkateshwar Rao Gannavarapu
2020-04-20 21:20 ` Venkateshwar Rao Gannavarapu
2020-04-20 21:20 ` [RFC PATCH 1/2] dt-bindings: display: xlnx: Add Xilinx DSI TX subsystem bindings Venkateshwar Rao Gannavarapu
2020-04-20 21:20 ` Venkateshwar Rao Gannavarapu
2020-04-25 20:29 ` Sam Ravnborg
2020-04-25 20:29 ` Sam Ravnborg
2020-04-30 18:36 ` Venkateshwar Rao Gannavarapu
2020-04-30 18:36 ` Venkateshwar Rao Gannavarapu
2020-05-24 2:59 ` Laurent Pinchart
2020-05-24 2:59 ` Laurent Pinchart
2020-04-20 21:20 ` [RFC PATCH 2/2] drm: xlnx: driver for Xilinx DSI TX Subsystem Venkateshwar Rao Gannavarapu
2020-04-20 21:20 ` Venkateshwar Rao Gannavarapu
2020-05-04 18:43 ` Hyun Kwon
2020-05-04 18:43 ` Hyun Kwon
2020-05-24 3:08 ` Laurent Pinchart
2020-05-24 3:08 ` Laurent Pinchart
2020-05-27 17:54 ` Hyun Kwon
2020-05-27 17:54 ` Hyun Kwon
2020-05-27 22:45 ` Laurent Pinchart
2020-05-27 22:45 ` Laurent Pinchart
2020-05-29 22:28 ` Hyun Kwon
2020-05-29 22:28 ` Hyun Kwon
2020-05-31 17:41 ` Venkateshwar Rao Gannavarapu
2020-05-31 17:41 ` Venkateshwar Rao Gannavarapu
2020-06-07 2:25 ` Laurent Pinchart [this message]
2020-06-07 2:25 ` Laurent Pinchart
2020-06-09 2:48 ` Venkateshwar Rao Gannavarapu
2020-06-09 2:48 ` Venkateshwar Rao Gannavarapu
2020-06-16 21:47 ` Laurent Pinchart
2020-06-16 21:47 ` Laurent Pinchart
2020-06-22 14:19 ` Venkateshwar Rao Gannavarapu
2020-06-22 14:19 ` Venkateshwar Rao Gannavarapu
2020-07-08 17:52 ` Laurent Pinchart
2020-07-08 17:52 ` Laurent Pinchart
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