From: Moritz Fischer <mdf@kernel.org>
To: Luca Ceresoli <luca@lucaceresoli.net>
Cc: linux-fpga@vger.kernel.org, Moritz Fischer <mdf@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Michal Simek <michal.simek@xilinx.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Anatolij Gustschin <agust@denx.de>
Subject: Re: [PATCH 1/5] dt-bindings: fpga: xilinx-slave-serial: valid for the 7 Series too
Date: Mon, 15 Jun 2020 21:42:04 -0700 [thread overview]
Message-ID: <20200616044202.GA46300@epycbox.lan> (raw)
In-Reply-To: <20200611211144.9421-1-luca@lucaceresoli.net>
On Thu, Jun 11, 2020 at 11:11:40PM +0200, Luca Ceresoli wrote:
> The Xilinx 7-series uses the same protocol, mention that.
>
> Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Acked-by: Moritz Fischer <mdf@kernel.org>
> ---
> .../devicetree/bindings/fpga/xilinx-slave-serial.txt | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt
> index cfa4ed42b62f..9f103f3872e8 100644
> --- a/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt
> +++ b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt
> @@ -1,11 +1,14 @@
> Xilinx Slave Serial SPI FPGA Manager
>
> -Xilinx Spartan-6 FPGAs support a method of loading the bitstream over
> -what is referred to as "slave serial" interface.
> +Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the
> +bitstream over what is referred to as "slave serial" interface.
> The slave serial link is not technically SPI, and might require extra
> circuits in order to play nicely with other SPI slaves on the same bus.
>
> -See https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
> +See:
> +- https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
> +- https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
> +- https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
>
> Required properties:
> - compatible: should contain "xlnx,fpga-slave-serial"
> --
> 2.27.0
>
WARNING: multiple messages have this Message-ID (diff)
From: Moritz Fischer <mdf@kernel.org>
To: Luca Ceresoli <luca@lucaceresoli.net>
Cc: devicetree@vger.kernel.org, linux-fpga@vger.kernel.org,
Michal Simek <michal.simek@xilinx.com>,
linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
Moritz Fischer <mdf@kernel.org>,
Anatolij Gustschin <agust@denx.de>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/5] dt-bindings: fpga: xilinx-slave-serial: valid for the 7 Series too
Date: Mon, 15 Jun 2020 21:42:02 -0700 [thread overview]
Message-ID: <20200616044202.GA46300@epycbox.lan> (raw)
In-Reply-To: <20200611211144.9421-1-luca@lucaceresoli.net>
On Thu, Jun 11, 2020 at 11:11:40PM +0200, Luca Ceresoli wrote:
> The Xilinx 7-series uses the same protocol, mention that.
>
> Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Acked-by: Moritz Fischer <mdf@kernel.org>
> ---
> .../devicetree/bindings/fpga/xilinx-slave-serial.txt | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt
> index cfa4ed42b62f..9f103f3872e8 100644
> --- a/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt
> +++ b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt
> @@ -1,11 +1,14 @@
> Xilinx Slave Serial SPI FPGA Manager
>
> -Xilinx Spartan-6 FPGAs support a method of loading the bitstream over
> -what is referred to as "slave serial" interface.
> +Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the
> +bitstream over what is referred to as "slave serial" interface.
> The slave serial link is not technically SPI, and might require extra
> circuits in order to play nicely with other SPI slaves on the same bus.
>
> -See https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
> +See:
> +- https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
> +- https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
> +- https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
>
> Required properties:
> - compatible: should contain "xlnx,fpga-slave-serial"
> --
> 2.27.0
>
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WARNING: multiple messages have this Message-ID (diff)
From: Moritz Fischer <mdf@kernel.org>
To: Luca Ceresoli <luca@lucaceresoli.net>
Cc: linux-fpga@vger.kernel.org, Moritz Fischer <mdf@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Michal Simek <michal.simek@xilinx.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Anatolij Gustschin <agust@denx.de>
Subject: Re: [PATCH 1/5] dt-bindings: fpga: xilinx-slave-serial: valid for the 7 Series too
Date: Mon, 15 Jun 2020 21:42:02 -0700 [thread overview]
Message-ID: <20200616044202.GA46300@epycbox.lan> (raw)
In-Reply-To: <20200611211144.9421-1-luca@lucaceresoli.net>
On Thu, Jun 11, 2020 at 11:11:40PM +0200, Luca Ceresoli wrote:
> The Xilinx 7-series uses the same protocol, mention that.
>
> Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Acked-by: Moritz Fischer <mdf@kernel.org>
> ---
> .../devicetree/bindings/fpga/xilinx-slave-serial.txt | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt
> index cfa4ed42b62f..9f103f3872e8 100644
> --- a/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt
> +++ b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt
> @@ -1,11 +1,14 @@
> Xilinx Slave Serial SPI FPGA Manager
>
> -Xilinx Spartan-6 FPGAs support a method of loading the bitstream over
> -what is referred to as "slave serial" interface.
> +Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the
> +bitstream over what is referred to as "slave serial" interface.
> The slave serial link is not technically SPI, and might require extra
> circuits in order to play nicely with other SPI slaves on the same bus.
>
> -See https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
> +See:
> +- https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
> +- https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
> +- https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
>
> Required properties:
> - compatible: should contain "xlnx,fpga-slave-serial"
> --
> 2.27.0
>
next prev parent reply other threads:[~2020-06-16 4:42 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-11 21:11 [PATCH 1/5] dt-bindings: fpga: xilinx-slave-serial: valid for the 7 Series too Luca Ceresoli
2020-06-11 21:11 ` Luca Ceresoli
2020-06-11 21:11 ` [PATCH 2/5] fpga manager: xilinx-spi: " Luca Ceresoli
2020-06-11 21:11 ` Luca Ceresoli
2020-06-19 1:38 ` Moritz Fischer
2020-06-19 1:38 ` Moritz Fischer
2020-06-19 1:38 ` Moritz Fischer
2020-06-11 21:11 ` [PATCH 3/5] fpga manager: xilinx-spi: remove unneeded, mistyped variables Luca Ceresoli
2020-06-11 21:11 ` Luca Ceresoli
2020-06-19 1:38 ` Moritz Fischer
2020-06-19 1:38 ` Moritz Fischer
2020-06-19 1:38 ` Moritz Fischer
2020-06-11 21:11 ` [PATCH 4/5] dt-bindings: fpga: xilinx-slave-serial: add optional INIT_B GPIO Luca Ceresoli
2020-06-11 21:11 ` Luca Ceresoli
2020-06-17 22:39 ` Rob Herring
2020-06-17 22:39 ` Rob Herring
2020-06-18 5:47 ` Luca Ceresoli
2020-06-18 5:47 ` Luca Ceresoli
2020-06-18 18:07 ` Rob Herring
2020-06-18 18:07 ` Rob Herring
2020-06-11 21:11 ` [PATCH 5/5] fpga manager: xilinx-spi: check INIT_B pin during write_init Luca Ceresoli
2020-06-11 21:11 ` Luca Ceresoli
2020-06-16 4:43 ` Moritz Fischer
2020-06-16 4:43 ` Moritz Fischer
2020-06-16 4:43 ` Moritz Fischer
2020-06-16 4:42 ` Moritz Fischer [this message]
2020-06-16 4:42 ` [PATCH 1/5] dt-bindings: fpga: xilinx-slave-serial: valid for the 7 Series too Moritz Fischer
2020-06-16 4:42 ` Moritz Fischer
2020-06-17 22:38 ` Rob Herring
2020-06-17 22:38 ` Rob Herring
2020-06-19 1:37 ` Moritz Fischer
2020-06-19 1:37 ` Moritz Fischer
2020-06-19 1:37 ` Moritz Fischer
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