Re: [PATCH 06/38] dt-bindings: display: tegra: Document display-hub

[Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>]

On Fri, Jun 12, 2020 at 04:18:31PM +0200, Thierry Reding wrote:
> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Tegra186 and later have an additional component in the display pipeline
> called the display hub. Document the bindings which were missing.

I'd rather this be after the conversion or I'm reviewing it twice.

> 
> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
>  .../display/tegra/nvidia,tegra20-host1x.txt   | 50 +++++++++++++++++++
>  1 file changed, 50 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
> index 47319214b5f6..2cf3cc4893da 100644
> --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
> +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
> @@ -297,6 +297,56 @@ of the following host1x client modules:
>    - reset-names: Must include the following entries:
>      - vic
>  
> +- display-hub: display controller hub
> +  Required properties:
> +  - compatible: "nvidia,tegra<chip>-display"
> +  - reg: Physical base address and length of the controller's registers.
> +  - interrupts: The interrupt outputs from the controller.
> +  - clocks: Must contain an entry for each entry in clock-names.
> +    See ../clocks/clock-bindings.txt for details.
> +  - clock-names: Must include the following entries:
> +    - disp
> +    - dsc
> +    - hub
> +  - resets: Must contain an entry for each entry in reset-names.
> +    See ../reset/reset.txt for details.
> +  - reset-names: Must include the following entries:
> +    - misc
> +    - wgrp0
> +    - wgrp1
> +    - wgrp2
> +    - wgrp3
> +    - wgrp4
> +    - wgrp5
> +  - power-domains: A list of phandle and specifiers identifying the power
> +    domains that the display hub is part of.
> +  - ranges: Range of registers used for the display controllers.
> +
> +  Each subnode of the display hub represents one of the display controllers
> +  available:
> +
> +  - display: display controller
> +    - compatible: "nvidia,tegra<chip>-dc"
> +    - reg: Physical base address and length of the controller's registers.
> +    - interrupts: The interrupt outputs from the controller.
> +    - clocks: Must contain an entry for each entry in clock-names.
> +      See ../clocks/clock-bindings.txt for details.
> +    - clock-names: Must include the following entries:
> +      - dc
> +    - resets: Must contain an entry for each entry in reset-names.
> +      See ../reset/reset.txt for details.
> +    - reset-names: Must include the following entries:
> +      - dc
> +    - power-domains: A list of phandle and specifiers that identify the power
> +      domains that this display controller is part of.
> +    - iommus: A phandle and specifier identifying the SMMU master interface of
> +      this display controller.
> +    - nvidia,outputs: A list of phandles of outputs that this display
> +      controller can drive.

Seems like an OF graph should describe this?

> +    - nvidia,head: The number of the display controller head. This is used to
> +      setup the various types of output to receive video data from the given
> +      head.

Not really clear what this is...

> +
>  Example:
>  
>  / {
> -- 
> 2.24.1
>