From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Subject: Re: [PATCH v6 1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD
Date: Thu, 18 Jun 2020 16:23:03 -0700 [thread overview]
Message-ID: <20200618232303.GB32149@intel.com> (raw)
In-Reply-To: <20200612230444.10121-2-manasi.d.navare@intel.com>
@Jani N, could you give an ACK on this if this looks okay, addressed
your review comments regarding the name of the function.
Else I have a r-b functionality wise so good to get merged?
Regards
Manasi
On Fri, Jun 12, 2020 at 04:04:42PM -0700, Manasi Navare wrote:
> DP sink device sets the Ignore MSA bit in its
> DP_DOWNSTREAM_PORT_COUNT register to indicate its ability to
> ignore the MSA video timing parameters and its ability to support
> seamless video timing change over a range of timing exposed by
> DisplayID and EDID.
> This is required for the sink to indicate that it is Adaptive sync
> capable.
>
> v3:
> * Fi the typo in commit message (Manasi)
> v2:
> * Rename to describe what the function does (Jani Nikula)
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Harry Wentland <harry.wentland@amd.com>
> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: Harry Wentland <harry.wentland@amd.com>
> ---
> include/drm/drm_dp_helper.h | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 1165ec105638..e47dc22ebf50 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1457,6 +1457,14 @@ drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> DP_ALTERNATE_SCRAMBLER_RESET_CAP;
> }
>
> +/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
> +static inline bool
> +drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> +{
> + return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
> + DP_MSA_TIMING_PAR_IGNORED;
> +}
> +
> /*
> * DisplayPort AUX channel
> */
> --
> 2.19.1
>
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WARNING: multiple messages have this Message-ID (diff)
From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Harry Wentland <harry.wentland@amd.com>,
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Subject: Re: [Intel-gfx] [PATCH v6 1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD
Date: Thu, 18 Jun 2020 16:23:03 -0700 [thread overview]
Message-ID: <20200618232303.GB32149@intel.com> (raw)
In-Reply-To: <20200612230444.10121-2-manasi.d.navare@intel.com>
@Jani N, could you give an ACK on this if this looks okay, addressed
your review comments regarding the name of the function.
Else I have a r-b functionality wise so good to get merged?
Regards
Manasi
On Fri, Jun 12, 2020 at 04:04:42PM -0700, Manasi Navare wrote:
> DP sink device sets the Ignore MSA bit in its
> DP_DOWNSTREAM_PORT_COUNT register to indicate its ability to
> ignore the MSA video timing parameters and its ability to support
> seamless video timing change over a range of timing exposed by
> DisplayID and EDID.
> This is required for the sink to indicate that it is Adaptive sync
> capable.
>
> v3:
> * Fi the typo in commit message (Manasi)
> v2:
> * Rename to describe what the function does (Jani Nikula)
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Harry Wentland <harry.wentland@amd.com>
> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: Harry Wentland <harry.wentland@amd.com>
> ---
> include/drm/drm_dp_helper.h | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 1165ec105638..e47dc22ebf50 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1457,6 +1457,14 @@ drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> DP_ALTERNATE_SCRAMBLER_RESET_CAP;
> }
>
> +/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
> +static inline bool
> +drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> +{
> + return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
> + DP_MSA_TIMING_PAR_IGNORED;
> +}
> +
> /*
> * DisplayPort AUX channel
> */
> --
> 2.19.1
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-06-18 23:21 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-12 23:04 [PATCH v6 0/3] VRR capable attach prop in i915, DPCD helper, VRR debugfs Manasi Navare
2020-06-12 23:04 ` [Intel-gfx] " Manasi Navare
2020-06-12 23:04 ` [PATCH v6 1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD Manasi Navare
2020-06-12 23:04 ` [Intel-gfx] " Manasi Navare
2020-06-18 23:23 ` Manasi Navare [this message]
2020-06-18 23:23 ` Manasi Navare
2020-06-12 23:04 ` [PATCH v6 2/3] drm/i915/dp: Attach and set drm connector VRR property Manasi Navare
2020-06-12 23:04 ` [Intel-gfx] " Manasi Navare
2020-06-12 23:04 ` [PATCH v6 3/3] drm/i915/dp: Expose connector VRR monitor range via debugfs Manasi Navare
2020-06-12 23:04 ` [Intel-gfx] " Manasi Navare
2020-06-12 23:56 ` [PATCH v7 " Manasi Navare
2020-06-12 23:56 ` [Intel-gfx] " Manasi Navare
2020-06-15 21:36 ` Emil Velikov
2020-06-15 21:36 ` [Intel-gfx] " Emil Velikov
2020-06-15 21:48 ` Manasi Navare
2020-06-15 21:48 ` [Intel-gfx] " Manasi Navare
2020-06-16 15:34 ` Emil Velikov
2020-06-16 15:34 ` [Intel-gfx] " Emil Velikov
2020-06-18 18:35 ` Manasi Navare
2020-06-18 18:35 ` [Intel-gfx] " Manasi Navare
2020-06-13 2:00 ` [Intel-gfx] [PATCH v6 " kernel test robot
2020-06-13 2:00 ` kernel test robot
2020-06-13 2:00 ` kernel test robot
2020-06-13 5:41 ` kernel test robot
2020-06-13 5:41 ` kernel test robot
2020-06-13 5:41 ` kernel test robot
2020-06-16 5:43 ` kernel test robot
2020-06-16 5:43 ` kernel test robot
2020-06-16 5:43 ` kernel test robot
2020-06-12 23:16 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for VRR capable attach prop in i915, DPCD helper, VRR debugfs Patchwork
2020-06-13 0:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for VRR capable attach prop in i915, DPCD helper, VRR debugfs (rev2) Patchwork
2020-06-13 0:09 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-06-13 0:39 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-06-19 21:11 ` [v6 0/3] VRR capable attach prop in i915, DPCD helper, VRR debugfs Bhanuprakash Modem
2020-06-19 21:11 ` [Intel-gfx] " Bhanuprakash Modem
2020-06-19 21:11 ` [v6 1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD Bhanuprakash Modem
2020-06-19 21:11 ` [Intel-gfx] " Bhanuprakash Modem
2020-06-19 21:11 ` [v6 2/3] drm/i915/dp: Attach and set drm connector VRR property Bhanuprakash Modem
2020-06-19 21:11 ` [Intel-gfx] " Bhanuprakash Modem
2020-06-19 21:11 ` [v8 3/3] drm/debug: Expose connector VRR monitor range via debugfs Bhanuprakash Modem
2020-06-19 21:11 ` [Intel-gfx] " Bhanuprakash Modem
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