All of lore.kernel.org
 help / color / mirror / Atom feed
From: Manasi Navare <manasi.d.navare@intel.com>
To: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [v6 1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD
Date: Fri, 19 Jun 2020 13:01:28 -0700	[thread overview]
Message-ID: <20200619200126.GA4176@intel.com> (raw)
In-Reply-To: <20200619212356.19285-2-bhanuprakash.modem@intel.com>

Thanks for the review, pushed to drm-misc

Manasi

On Sat, Jun 20, 2020 at 02:53:54AM +0530, Bhanuprakash Modem wrote:
> From: Manasi Navare <manasi.d.navare@intel.com>
> 
> DP sink device sets the Ignore MSA bit in its
> DP_DOWNSTREAM_PORT_COUNT register to indicate its ability to
> ignore the MSA video timing parameters and its ability to support
> seamless video timing change over a range of timing exposed by
> DisplayID and EDID.
> This is required for the sink to indicate that it is Adaptive sync
> capable.
> 
> v3:
> * Fi the typo in commit message (Manasi)
> v2:
> * Rename to describe what the function does (Jani Nikula)
> 
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Harry Wentland <harry.wentland@amd.com>
> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: Harry Wentland <harry.wentland@amd.com>
> ---
>  include/drm/drm_dp_helper.h | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 1165ec105638..e47dc22ebf50 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1457,6 +1457,14 @@ drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
>  			DP_ALTERNATE_SCRAMBLER_RESET_CAP;
>  }
>  
> +/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
> +static inline bool
> +drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> +{
> +	return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
> +		DP_MSA_TIMING_PAR_IGNORED;
> +}
> +
>  /*
>   * DisplayPort AUX channel
>   */
> -- 
> 2.20.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

WARNING: multiple messages have this Message-ID (diff)
From: Manasi Navare <manasi.d.navare@intel.com>
To: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [v6 1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD
Date: Fri, 19 Jun 2020 13:01:28 -0700	[thread overview]
Message-ID: <20200619200126.GA4176@intel.com> (raw)
In-Reply-To: <20200619212356.19285-2-bhanuprakash.modem@intel.com>

Thanks for the review, pushed to drm-misc

Manasi

On Sat, Jun 20, 2020 at 02:53:54AM +0530, Bhanuprakash Modem wrote:
> From: Manasi Navare <manasi.d.navare@intel.com>
> 
> DP sink device sets the Ignore MSA bit in its
> DP_DOWNSTREAM_PORT_COUNT register to indicate its ability to
> ignore the MSA video timing parameters and its ability to support
> seamless video timing change over a range of timing exposed by
> DisplayID and EDID.
> This is required for the sink to indicate that it is Adaptive sync
> capable.
> 
> v3:
> * Fi the typo in commit message (Manasi)
> v2:
> * Rename to describe what the function does (Jani Nikula)
> 
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Harry Wentland <harry.wentland@amd.com>
> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: Harry Wentland <harry.wentland@amd.com>
> ---
>  include/drm/drm_dp_helper.h | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 1165ec105638..e47dc22ebf50 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1457,6 +1457,14 @@ drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
>  			DP_ALTERNATE_SCRAMBLER_RESET_CAP;
>  }
>  
> +/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
> +static inline bool
> +drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> +{
> +	return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
> +		DP_MSA_TIMING_PAR_IGNORED;
> +}
> +
>  /*
>   * DisplayPort AUX channel
>   */
> -- 
> 2.20.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2020-06-19 20:00 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-19 21:23 [v6 0/3] VRR capable attach prop in i915, DPCD helper, VRR debugfs Bhanuprakash Modem
2020-06-19 21:23 ` [Intel-gfx] " Bhanuprakash Modem
2020-06-19 14:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for VRR capable attach prop in i915, DPCD helper, VRR debugfs (rev3) Patchwork
2020-06-19 14:45 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-06-19 15:13 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-06-19 21:23 ` [v6 1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD Bhanuprakash Modem
2020-06-19 21:23   ` [Intel-gfx] " Bhanuprakash Modem
2020-06-19 20:01   ` Manasi Navare [this message]
2020-06-19 20:01     ` Manasi Navare
2020-06-19 21:23 ` [v6 2/3] drm/i915/dp: Attach and set drm connector VRR property Bhanuprakash Modem
2020-06-19 21:23   ` [Intel-gfx] " Bhanuprakash Modem
2020-06-19 21:23 ` [v8 3/3] drm/debug: Expose connector VRR monitor range via debugfs Bhanuprakash Modem
2020-06-19 21:23   ` [Intel-gfx] " Bhanuprakash Modem
2020-06-19 18:42   ` Manasi Navare
2020-06-19 18:42     ` [Intel-gfx] " Manasi Navare
2020-06-22  4:34     ` Modem, Bhanuprakash
2020-06-22  4:34       ` [Intel-gfx] " Modem, Bhanuprakash
  -- strict thread matches above, loose matches on Subject: below --
2020-06-12 23:04 [PATCH v6 0/3] VRR capable attach prop in i915, DPCD helper, VRR debugfs Manasi Navare
2020-06-19 21:11 ` [Intel-gfx] [v6 1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD Bhanuprakash Modem

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200619200126.GA4176@intel.com \
    --to=manasi.d.navare@intel.com \
    --cc=bhanuprakash.modem@intel.com \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.