From: Christoph Hellwig <hch@lst.de>
To: Baolin Wang <baolin.wang@linux.alibaba.com>
Cc: sagi@grimberg.me, linux-kernel@vger.kernel.org,
linux-nvme@lists.infradead.org, axboe@fb.com,
baolin.wang7@gmail.com, kbusch@kernel.org, hch@lst.de
Subject: Re: [PATCH 2/3] nvme-pci: Add controller memory buffer supported macro
Date: Tue, 23 Jun 2020 18:27:51 +0200 [thread overview]
Message-ID: <20200623162751.GA4846@lst.de> (raw)
In-Reply-To: <eab18c7696ea0e34a6ab0371d7d17ad45d1566ce.1592916850.git.baolin.wang@linux.alibaba.com>
On Tue, Jun 23, 2020 at 09:24:33PM +0800, Baolin Wang wrote:
> Introduce a new capability macro to indicate if the controller
> supports the memory buffer or not, instead of reading the
> NVME_REG_CMBSZ register.
This is a complex issue. The CMBS bit was only added in NVMe 1.4 as
a backwards incompatible change, as the CMB addressing scheme can lead
to data corruption. The CMBS was added as part of the horribe hack
that also involves the CBA field, which we'll need to see before
using it to work around the addressing issue. At the same time we
should also continue supporting the legacy pre-1.4 CMB with a warning
(and may reject it if we know we run in a VM).
_______________________________________________
Linux-nvme mailing list
Linux-nvme@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-nvme
WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@lst.de>
To: Baolin Wang <baolin.wang@linux.alibaba.com>
Cc: kbusch@kernel.org, axboe@fb.com, hch@lst.de, sagi@grimberg.me,
baolin.wang7@gmail.com, linux-nvme@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/3] nvme-pci: Add controller memory buffer supported macro
Date: Tue, 23 Jun 2020 18:27:51 +0200 [thread overview]
Message-ID: <20200623162751.GA4846@lst.de> (raw)
In-Reply-To: <eab18c7696ea0e34a6ab0371d7d17ad45d1566ce.1592916850.git.baolin.wang@linux.alibaba.com>
On Tue, Jun 23, 2020 at 09:24:33PM +0800, Baolin Wang wrote:
> Introduce a new capability macro to indicate if the controller
> supports the memory buffer or not, instead of reading the
> NVME_REG_CMBSZ register.
This is a complex issue. The CMBS bit was only added in NVMe 1.4 as
a backwards incompatible change, as the CMB addressing scheme can lead
to data corruption. The CMBS was added as part of the horribe hack
that also involves the CBA field, which we'll need to see before
using it to work around the addressing issue. At the same time we
should also continue supporting the legacy pre-1.4 CMB with a warning
(and may reject it if we know we run in a VM).
next prev parent reply other threads:[~2020-06-23 16:28 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-23 13:24 [PATCH 0/3] Some improvements for NVMe Baolin Wang
2020-06-23 13:24 ` [PATCH 1/3] nvme: Add Arbitration Burst support Baolin Wang
2020-06-23 14:40 ` Keith Busch
2020-06-23 14:40 ` Keith Busch
2020-06-23 17:39 ` Sagi Grimberg
2020-06-23 17:39 ` Sagi Grimberg
2020-06-23 18:01 ` Keith Busch
2020-06-23 18:01 ` Keith Busch
2020-06-24 1:34 ` Baolin Wang
2020-06-24 1:34 ` Baolin Wang
2020-06-24 2:51 ` Keith Busch
2020-06-24 2:51 ` Keith Busch
2020-06-24 2:54 ` Baolin Wang
2020-06-24 2:54 ` Baolin Wang
2020-06-24 2:57 ` Keith Busch
2020-06-24 2:57 ` Keith Busch
2020-06-24 3:06 ` Baolin Wang
2020-06-24 3:06 ` Baolin Wang
2020-06-23 13:24 ` [PATCH 2/3] nvme-pci: Add controller memory buffer supported macro Baolin Wang
2020-06-23 16:27 ` Christoph Hellwig [this message]
2020-06-23 16:27 ` Christoph Hellwig
2020-06-24 2:07 ` Baolin Wang
2020-06-24 2:07 ` Baolin Wang
2020-06-24 6:22 ` Baolin Wang
2020-06-24 2:58 ` Keith Busch
2020-06-24 2:58 ` Keith Busch
2020-06-24 5:47 ` Christoph Hellwig
2020-06-24 5:47 ` Christoph Hellwig
2020-06-23 13:24 ` [PATCH 3/3] nvme: Use USEC_PER_SEC instead of magic numbers Baolin Wang
2020-06-23 17:39 ` Sagi Grimberg
2020-06-23 17:39 ` Sagi Grimberg
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