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From: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Thierry Reding
	<thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	Jonathan Hunter
	<jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
	Mikko Perttunen <cyndis-/1wQRMveznE@public.gmane.org>
Cc: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: [PATCH v2 2/6] drm/tegra: gr2d: Add tiled PATBASE address register
Date: Mon, 29 Jun 2020 06:18:38 +0300	[thread overview]
Message-ID: <20200629031842.32463-3-digetx@gmail.com> (raw)
In-Reply-To: <20200629031842.32463-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

There are two PATBASE address registers, one for linear layout and other
for tiled. The driver's address registers list misses the tiled PATBASE
register.

Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 drivers/gpu/drm/tegra/gr2d.c | 1 +
 drivers/gpu/drm/tegra/gr2d.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/tegra/gr2d.c b/drivers/gpu/drm/tegra/gr2d.c
index 48363f744bb9..1a0d3ba6e525 100644
--- a/drivers/gpu/drm/tegra/gr2d.c
+++ b/drivers/gpu/drm/tegra/gr2d.c
@@ -177,6 +177,7 @@ static const u32 gr2d_addr_regs[] = {
 	GR2D_DSTC_BASE_ADDR,
 	GR2D_SRCA_BASE_ADDR,
 	GR2D_SRCB_BASE_ADDR,
+	GR2D_PATBASE_ADDR,
 	GR2D_SRC_BASE_ADDR_SB,
 	GR2D_DSTA_BASE_ADDR_SB,
 	GR2D_DSTB_BASE_ADDR_SB,
diff --git a/drivers/gpu/drm/tegra/gr2d.h b/drivers/gpu/drm/tegra/gr2d.h
index 2398486f0699..9b7d66e15b9f 100644
--- a/drivers/gpu/drm/tegra/gr2d.h
+++ b/drivers/gpu/drm/tegra/gr2d.h
@@ -14,6 +14,7 @@
 #define GR2D_DSTC_BASE_ADDR		0x2d
 #define GR2D_SRCA_BASE_ADDR		0x31
 #define GR2D_SRCB_BASE_ADDR		0x32
+#define GR2D_PATBASE_ADDR		0x47
 #define GR2D_SRC_BASE_ADDR_SB		0x48
 #define GR2D_DSTA_BASE_ADDR_SB		0x49
 #define GR2D_DSTB_BASE_ADDR_SB		0x4a
-- 
2.26.0

WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Mikko Perttunen <cyndis@kapsi.fi>
Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org
Subject: [PATCH v2 2/6] drm/tegra: gr2d: Add tiled PATBASE address register
Date: Mon, 29 Jun 2020 06:18:38 +0300	[thread overview]
Message-ID: <20200629031842.32463-3-digetx@gmail.com> (raw)
In-Reply-To: <20200629031842.32463-1-digetx@gmail.com>

There are two PATBASE address registers, one for linear layout and other
for tiled. The driver's address registers list misses the tiled PATBASE
register.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/gpu/drm/tegra/gr2d.c | 1 +
 drivers/gpu/drm/tegra/gr2d.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/tegra/gr2d.c b/drivers/gpu/drm/tegra/gr2d.c
index 48363f744bb9..1a0d3ba6e525 100644
--- a/drivers/gpu/drm/tegra/gr2d.c
+++ b/drivers/gpu/drm/tegra/gr2d.c
@@ -177,6 +177,7 @@ static const u32 gr2d_addr_regs[] = {
 	GR2D_DSTC_BASE_ADDR,
 	GR2D_SRCA_BASE_ADDR,
 	GR2D_SRCB_BASE_ADDR,
+	GR2D_PATBASE_ADDR,
 	GR2D_SRC_BASE_ADDR_SB,
 	GR2D_DSTA_BASE_ADDR_SB,
 	GR2D_DSTB_BASE_ADDR_SB,
diff --git a/drivers/gpu/drm/tegra/gr2d.h b/drivers/gpu/drm/tegra/gr2d.h
index 2398486f0699..9b7d66e15b9f 100644
--- a/drivers/gpu/drm/tegra/gr2d.h
+++ b/drivers/gpu/drm/tegra/gr2d.h
@@ -14,6 +14,7 @@
 #define GR2D_DSTC_BASE_ADDR		0x2d
 #define GR2D_SRCA_BASE_ADDR		0x31
 #define GR2D_SRCB_BASE_ADDR		0x32
+#define GR2D_PATBASE_ADDR		0x47
 #define GR2D_SRC_BASE_ADDR_SB		0x48
 #define GR2D_DSTA_BASE_ADDR_SB		0x49
 #define GR2D_DSTB_BASE_ADDR_SB		0x4a
-- 
2.26.0

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  parent reply	other threads:[~2020-06-29  3:18 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-29  3:18 [PATCH v2 0/6] Tegra DRM / Host1x drivers improvements and corrections Dmitry Osipenko
2020-06-29  3:18 ` Dmitry Osipenko
     [not found] ` <20200629031842.32463-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-06-29  3:18   ` [PATCH v2 1/6] drm/tegra: gr3d: Assert reset before power-gating Dmitry Osipenko
2020-06-29  3:18     ` Dmitry Osipenko
2020-06-29  3:18   ` Dmitry Osipenko [this message]
2020-06-29  3:18     ` [PATCH v2 2/6] drm/tegra: gr2d: Add tiled PATBASE address register Dmitry Osipenko
2020-06-29  3:18   ` [PATCH v2 3/6] gpu: host1x: Optimize BOs usage when firewall is enabled Dmitry Osipenko
2020-06-29  3:18     ` Dmitry Osipenko
2020-06-29  3:18   ` [PATCH v2 4/6] gpu: host1x: Put gather's BO on pinning error Dmitry Osipenko
2020-06-29  3:18     ` Dmitry Osipenko
2020-06-29  3:18   ` [PATCH v2 5/6] gpu: host1x: debug: Fix multiple channels emitting messages simultaneously Dmitry Osipenko
2020-06-29  3:18     ` Dmitry Osipenko
2020-06-29  3:18   ` [PATCH v2 6/6] gpu: host1x: debug: Dump push buffer state Dmitry Osipenko
2020-06-29  3:18     ` Dmitry Osipenko

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