* [Intel-gfx] [PATCH 1/2] drm/i915: Enable TPS3/4 on all platforms that support them
@ 2020-07-02 18:24 Ville Syrjala
2020-07-02 18:24 ` [Intel-gfx] [PATCH 2/2] drm/i915: Fix the training pattern debug print Ville Syrjala
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: Ville Syrjala @ 2020-07-02 18:24 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Stop using HBR2/3 support as a proxy for TPS3/4 support.
The two are no longer 1:1 in the hardware, arguably they
never were due to HSW ULX which does support TPS3 while
being limited to HBR1.
In more recent times GLK gained support for TPS4 while
being limited to HBR2. And on CNL+ some ports support
HBR3 while others are limited to HBR2, but all ports
support TPS4.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 12 +++-----
drivers/gpu/drm/i915/display/intel_dp.h | 4 +--
.../drm/i915/display/intel_dp_link_training.c | 29 +++++++------------
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
4 files changed, 17 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c9b93c5706af..5ac182357fc9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1799,18 +1799,14 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
intel_dp->aux.transfer = intel_dp_aux_transfer;
}
-bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
+bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
{
- int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
-
- return max_rate >= 540000;
+ return INTEL_GEN(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
}
-bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
+bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
{
- int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
-
- return max_rate >= 810000;
+ return INTEL_GEN(i915) >= 10 || IS_GEMINILAKE(i915);
}
static void
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 0a8950f744f6..d597a9848397 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -94,8 +94,8 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp);
void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
u8 *link_bw, u8 *rate_select);
-bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
-bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
+bool intel_dp_source_supports_tps3(struct drm_i915_private *i915);
+bool intel_dp_source_supports_tps4(struct drm_i915_private *i915);
bool
intel_dp_get_link_status(struct intel_dp *intel_dp, u8 *link_status);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 2493142a70e9..57c2089c9f5a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -259,41 +259,32 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
*/
static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
bool source_tps3, sink_tps3, source_tps4, sink_tps4;
- /*
- * Intel platforms that support HBR3 also support TPS4. It is mandatory
- * for all downstream devices that support HBR3. There are no known eDP
- * panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1
- * specification.
- */
- source_tps4 = intel_dp_source_supports_hbr3(intel_dp);
+ source_tps4 = intel_dp_source_supports_tps4(i915);
sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd);
if (source_tps4 && sink_tps4) {
return DP_TRAINING_PATTERN_4;
} else if (intel_dp->link_rate == 810000) {
if (!source_tps4)
- drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
- "8.1 Gbps link rate without source HBR3/TPS4 support\n");
+ drm_dbg_kms(&i915->drm,
+ "8.1 Gbps link rate without source TPS4 support\n");
if (!sink_tps4)
- drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
+ drm_dbg_kms(&i915->drm,
"8.1 Gbps link rate without sink TPS4 support\n");
}
- /*
- * Intel platforms that support HBR2 also support TPS3. TPS3 support is
- * also mandatory for downstream devices that support HBR2. However, not
- * all sinks follow the spec.
- */
- source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
+
+ source_tps3 = intel_dp_source_supports_tps3(i915);
sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
if (source_tps3 && sink_tps3) {
return DP_TRAINING_PATTERN_3;
} else if (intel_dp->link_rate >= 540000) {
if (!source_tps3)
- drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
- ">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n");
+ drm_dbg_kms(&i915->drm,
+ ">=5.4/6.48 Gbps link rate without source TPS3 support\n");
if (!sink_tps3)
- drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
+ drm_dbg_kms(&i915->drm,
">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 611cb8d74811..5ba1aa2c6748 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -451,7 +451,7 @@ static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
val |= EDP_PSR_TP2_TP3_TIME_2500us;
check_tp3_sel:
- if (intel_dp_source_supports_hbr2(intel_dp) &&
+ if (intel_dp_source_supports_tps3(dev_priv) &&
drm_dp_tps3_supported(intel_dp->dpcd))
val |= EDP_PSR_TP1_TP3_SEL;
else
--
2.26.2
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^ permalink raw reply related [flat|nested] 8+ messages in thread* [Intel-gfx] [PATCH 2/2] drm/i915: Fix the training pattern debug print 2020-07-02 18:24 [Intel-gfx] [PATCH 1/2] drm/i915: Enable TPS3/4 on all platforms that support them Ville Syrjala @ 2020-07-02 18:24 ` Ville Syrjala 2020-07-02 19:27 ` Manasi Navare 2020-07-02 19:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: Enable TPS3/4 on all platforms that support them Patchwork ` (3 subsequent siblings) 4 siblings, 1 reply; 8+ messages in thread From: Ville Syrjala @ 2020-07-02 18:24 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Currently we claim to use TPS7 when using TPS4. That is just confusing, so let's fix the debug print. And while we're touching this let's add the customary encoder id/name as well. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 26 ++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 5ac182357fc9..eba97b1f5839 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4353,17 +4353,33 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp) intel_dp->set_signal_levels(intel_dp); } +static char dp_training_pattern_name(u8 train_pat) +{ + switch (train_pat) { + case DP_TRAINING_PATTERN_1: + case DP_TRAINING_PATTERN_2: + case DP_TRAINING_PATTERN_3: + return '0' + train_pat; + case DP_TRAINING_PATTERN_4: + return '4'; + default: + return '?'; + } +} + void intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, u8 dp_train_pat) { - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd); + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + u8 train_pat = dp_train_pat & drm_dp_training_pattern_mask(intel_dp->dpcd); - if (dp_train_pat & train_pat_mask) + if (train_pat) drm_dbg_kms(&dev_priv->drm, - "Using DP training pattern TPS%d\n", - dp_train_pat & train_pat_mask); + "[ENCODER:%d:%s] Using DP training pattern TPS%c\n", + encoder->base.base.id, encoder->base.name, + dp_training_pattern_name(train_pat)); intel_dp->set_link_train(intel_dp, dp_train_pat); } -- 2.26.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915: Fix the training pattern debug print 2020-07-02 18:24 ` [Intel-gfx] [PATCH 2/2] drm/i915: Fix the training pattern debug print Ville Syrjala @ 2020-07-02 19:27 ` Manasi Navare 2020-07-03 10:56 ` Ville Syrjälä 0 siblings, 1 reply; 8+ messages in thread From: Manasi Navare @ 2020-07-02 19:27 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx On Thu, Jul 02, 2020 at 09:24:50PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Currently we claim to use TPS7 when using TPS4. That is just > confusing, so let's fix the debug print. > > And while we're touching this let's add the customary > encoder id/name as well. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 26 ++++++++++++++++++++----- > 1 file changed, 21 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 5ac182357fc9..eba97b1f5839 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -4353,17 +4353,33 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp) > intel_dp->set_signal_levels(intel_dp); > } > > +static char dp_training_pattern_name(u8 train_pat) > +{ > + switch (train_pat) { > + case DP_TRAINING_PATTERN_1: > + case DP_TRAINING_PATTERN_2: > + case DP_TRAINING_PATTERN_3: > + return '0' + train_pat; > + case DP_TRAINING_PATTERN_4: > + return '4'; > + default: > + return '?'; Shouldnt this be a WARN? If we just return a ? it might result into failure without any warn Other than that I like that now it will say TPS4 instead of misleading TPS7 So with a default WARN, Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Manasi > + } > +} > + > void > intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, > u8 dp_train_pat) > { > - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > - u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd); > + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + u8 train_pat = dp_train_pat & drm_dp_training_pattern_mask(intel_dp->dpcd); > > - if (dp_train_pat & train_pat_mask) > + if (train_pat) > drm_dbg_kms(&dev_priv->drm, > - "Using DP training pattern TPS%d\n", > - dp_train_pat & train_pat_mask); > + "[ENCODER:%d:%s] Using DP training pattern TPS%c\n", > + encoder->base.base.id, encoder->base.name, > + dp_training_pattern_name(train_pat)); > > intel_dp->set_link_train(intel_dp, dp_train_pat); > } > -- > 2.26.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915: Fix the training pattern debug print 2020-07-02 19:27 ` Manasi Navare @ 2020-07-03 10:56 ` Ville Syrjälä 0 siblings, 0 replies; 8+ messages in thread From: Ville Syrjälä @ 2020-07-03 10:56 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx On Thu, Jul 02, 2020 at 12:27:42PM -0700, Manasi Navare wrote: > On Thu, Jul 02, 2020 at 09:24:50PM +0300, Ville Syrjala wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > Currently we claim to use TPS7 when using TPS4. That is just > > confusing, so let's fix the debug print. > > > > And while we're touching this let's add the customary > > encoder id/name as well. > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_dp.c | 26 ++++++++++++++++++++----- > > 1 file changed, 21 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > > index 5ac182357fc9..eba97b1f5839 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -4353,17 +4353,33 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp) > > intel_dp->set_signal_levels(intel_dp); > > } > > > > +static char dp_training_pattern_name(u8 train_pat) > > +{ > > + switch (train_pat) { > > + case DP_TRAINING_PATTERN_1: > > + case DP_TRAINING_PATTERN_2: > > + case DP_TRAINING_PATTERN_3: > > + return '0' + train_pat; > > + case DP_TRAINING_PATTERN_4: > > + return '4'; > > + default: > > + return '?'; > > Shouldnt this be a WARN? If we just return a ? it might result into failure without any warn Only if decide that this functions's purpose is to validate the rest of the code isn't broken and using bogus training patterns. > > Other than that I like that now it will say TPS4 instead of misleading TPS7 > So with a default WARN, > > Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> > > Manasi > > > + } > > +} > > + > > void > > intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, > > u8 dp_train_pat) > > { > > - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > - u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd); > > + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > + u8 train_pat = dp_train_pat & drm_dp_training_pattern_mask(intel_dp->dpcd); > > > > - if (dp_train_pat & train_pat_mask) > > + if (train_pat) > > drm_dbg_kms(&dev_priv->drm, > > - "Using DP training pattern TPS%d\n", > > - dp_train_pat & train_pat_mask); > > + "[ENCODER:%d:%s] Using DP training pattern TPS%c\n", > > + encoder->base.base.id, encoder->base.name, > > + dp_training_pattern_name(train_pat)); > > > > intel_dp->set_link_train(intel_dp, dp_train_pat); > > } > > -- > > 2.26.2 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: Enable TPS3/4 on all platforms that support them 2020-07-02 18:24 [Intel-gfx] [PATCH 1/2] drm/i915: Enable TPS3/4 on all platforms that support them Ville Syrjala 2020-07-02 18:24 ` [Intel-gfx] [PATCH 2/2] drm/i915: Fix the training pattern debug print Ville Syrjala @ 2020-07-02 19:37 ` Patchwork 2020-07-02 20:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork ` (2 subsequent siblings) 4 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2020-07-02 19:37 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915: Enable TPS3/4 on all platforms that support them URL : https://patchwork.freedesktop.org/series/79060/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1223:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1226:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1229:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1232:22: error: Expected constant expression in case statement _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Enable TPS3/4 on all platforms that support them 2020-07-02 18:24 [Intel-gfx] [PATCH 1/2] drm/i915: Enable TPS3/4 on all platforms that support them Ville Syrjala 2020-07-02 18:24 ` [Intel-gfx] [PATCH 2/2] drm/i915: Fix the training pattern debug print Ville Syrjala 2020-07-02 19:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: Enable TPS3/4 on all platforms that support them Patchwork @ 2020-07-02 20:00 ` Patchwork 2020-07-02 22:38 ` [Intel-gfx] [PATCH 1/2] " Manasi Navare 2020-07-03 1:37 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] " Patchwork 4 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2020-07-02 20:00 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915: Enable TPS3/4 on all platforms that support them URL : https://patchwork.freedesktop.org/series/79060/ State : success == Summary == CI Bug Log - changes from CI_DRM_8698 -> Patchwork_18072 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/index.html Known issues ------------ Here are the changes found in Patchwork_18072 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@kms_busy@basic@flip: - fi-kbl-x1275: [PASS][1] -> [DMESG-WARN][2] ([i915#62] / [i915#92] / [i915#95]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/fi-kbl-x1275/igt@kms_busy@basic@flip.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/fi-kbl-x1275/igt@kms_busy@basic@flip.html * igt@kms_cursor_legacy@basic-flip-before-cursor-legacy: - fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html #### Possible fixes #### * igt@i915_pm_backlight@basic-brightness: - fi-whl-u: [DMESG-WARN][5] ([i915#95]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/fi-whl-u/igt@i915_pm_backlight@basic-brightness.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/fi-whl-u/igt@i915_pm_backlight@basic-brightness.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html * igt@i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/fi-glk-dsi/igt@i915_pm_rpm@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/fi-glk-dsi/igt@i915_pm_rpm@module-reload.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - {fi-kbl-7560u}: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Warnings #### * igt@i915_pm_rpm@module-reload: - fi-kbl-x1275: [DMESG-FAIL][13] ([i915#62]) -> [SKIP][14] ([fdo#109271]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html * igt@kms_cursor_legacy@basic-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html * igt@kms_flip@basic-plain-flip@a-dp1: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/fi-kbl-x1275/igt@kms_flip@basic-plain-flip@a-dp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/fi-kbl-x1275/igt@kms_flip@basic-plain-flip@a-dp1.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (43 -> 37) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8698 -> Patchwork_18072 CI-20190529: 20190529 CI_DRM_8698: a5bde2bddb64dc774e9fc1444243b8f224a31df6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5720: f35053d4b6d7bbcf6505ef67a8bd56acc7fb2eb2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18072: 1ebdc2b628a91ef273b09fa246fc66b5cc4a2fee @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 1ebdc2b628a9 drm/i915: Fix the training pattern debug print 584f55268f38 drm/i915: Enable TPS3/4 on all platforms that support them == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Enable TPS3/4 on all platforms that support them 2020-07-02 18:24 [Intel-gfx] [PATCH 1/2] drm/i915: Enable TPS3/4 on all platforms that support them Ville Syrjala ` (2 preceding siblings ...) 2020-07-02 20:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2020-07-02 22:38 ` Manasi Navare 2020-07-03 1:37 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] " Patchwork 4 siblings, 0 replies; 8+ messages in thread From: Manasi Navare @ 2020-07-02 22:38 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx On Thu, Jul 02, 2020 at 09:24:49PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Stop using HBR2/3 support as a proxy for TPS3/4 support. > The two are no longer 1:1 in the hardware, arguably they > never were due to HSW ULX which does support TPS3 while > being limited to HBR1. > > In more recent times GLK gained support for TPS4 while > being limited to HBR2. And on CNL+ some ports support > HBR3 while others are limited to HBR2, but all ports > support TPS4. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Makes sense to me Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Manasi > --- > drivers/gpu/drm/i915/display/intel_dp.c | 12 +++----- > drivers/gpu/drm/i915/display/intel_dp.h | 4 +-- > .../drm/i915/display/intel_dp_link_training.c | 29 +++++++------------ > drivers/gpu/drm/i915/display/intel_psr.c | 2 +- > 4 files changed, 17 insertions(+), 30 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index c9b93c5706af..5ac182357fc9 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -1799,18 +1799,14 @@ intel_dp_aux_init(struct intel_dp *intel_dp) > intel_dp->aux.transfer = intel_dp_aux_transfer; > } > > -bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) > +bool intel_dp_source_supports_tps3(struct drm_i915_private *i915) > { > - int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1]; > - > - return max_rate >= 540000; > + return INTEL_GEN(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915); > } > > -bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp) > +bool intel_dp_source_supports_tps4(struct drm_i915_private *i915) > { > - int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1]; > - > - return max_rate >= 810000; > + return INTEL_GEN(i915) >= 10 || IS_GEMINILAKE(i915); > } > > static void > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h > index 0a8950f744f6..d597a9848397 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.h > +++ b/drivers/gpu/drm/i915/display/intel_dp.h > @@ -94,8 +94,8 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp); > void intel_dp_set_idle_link_train(struct intel_dp *intel_dp); > void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, > u8 *link_bw, u8 *rate_select); > -bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp); > -bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp); > +bool intel_dp_source_supports_tps3(struct drm_i915_private *i915); > +bool intel_dp_source_supports_tps4(struct drm_i915_private *i915); > bool > intel_dp_get_link_status(struct intel_dp *intel_dp, u8 *link_status); > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > index 2493142a70e9..57c2089c9f5a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > @@ -259,41 +259,32 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) > */ > static u32 intel_dp_training_pattern(struct intel_dp *intel_dp) > { > + struct drm_i915_private *i915 = dp_to_i915(intel_dp); > bool source_tps3, sink_tps3, source_tps4, sink_tps4; > > - /* > - * Intel platforms that support HBR3 also support TPS4. It is mandatory > - * for all downstream devices that support HBR3. There are no known eDP > - * panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 > - * specification. > - */ > - source_tps4 = intel_dp_source_supports_hbr3(intel_dp); > + source_tps4 = intel_dp_source_supports_tps4(i915); > sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd); > if (source_tps4 && sink_tps4) { > return DP_TRAINING_PATTERN_4; > } else if (intel_dp->link_rate == 810000) { > if (!source_tps4) > - drm_dbg_kms(&dp_to_i915(intel_dp)->drm, > - "8.1 Gbps link rate without source HBR3/TPS4 support\n"); > + drm_dbg_kms(&i915->drm, > + "8.1 Gbps link rate without source TPS4 support\n"); > if (!sink_tps4) > - drm_dbg_kms(&dp_to_i915(intel_dp)->drm, > + drm_dbg_kms(&i915->drm, > "8.1 Gbps link rate without sink TPS4 support\n"); > } > - /* > - * Intel platforms that support HBR2 also support TPS3. TPS3 support is > - * also mandatory for downstream devices that support HBR2. However, not > - * all sinks follow the spec. > - */ > - source_tps3 = intel_dp_source_supports_hbr2(intel_dp); > + > + source_tps3 = intel_dp_source_supports_tps3(i915); > sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd); > if (source_tps3 && sink_tps3) { > return DP_TRAINING_PATTERN_3; > } else if (intel_dp->link_rate >= 540000) { > if (!source_tps3) > - drm_dbg_kms(&dp_to_i915(intel_dp)->drm, > - ">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n"); > + drm_dbg_kms(&i915->drm, > + ">=5.4/6.48 Gbps link rate without source TPS3 support\n"); > if (!sink_tps3) > - drm_dbg_kms(&dp_to_i915(intel_dp)->drm, > + drm_dbg_kms(&i915->drm, > ">=5.4/6.48 Gbps link rate without sink TPS3 support\n"); > } > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index 611cb8d74811..5ba1aa2c6748 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -451,7 +451,7 @@ static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) > val |= EDP_PSR_TP2_TP3_TIME_2500us; > > check_tp3_sel: > - if (intel_dp_source_supports_hbr2(intel_dp) && > + if (intel_dp_source_supports_tps3(dev_priv) && > drm_dp_tps3_supported(intel_dp->dpcd)) > val |= EDP_PSR_TP1_TP3_SEL; > else > -- > 2.26.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: Enable TPS3/4 on all platforms that support them 2020-07-02 18:24 [Intel-gfx] [PATCH 1/2] drm/i915: Enable TPS3/4 on all platforms that support them Ville Syrjala ` (3 preceding siblings ...) 2020-07-02 22:38 ` [Intel-gfx] [PATCH 1/2] " Manasi Navare @ 2020-07-03 1:37 ` Patchwork 4 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2020-07-03 1:37 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915: Enable TPS3/4 on all platforms that support them URL : https://patchwork.freedesktop.org/series/79060/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8698_full -> Patchwork_18072_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_18072_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18072_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18072_full: ### IGT changes ### #### Possible regressions #### * igt@i915_pm_rps@reset: - shard-skl: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-skl7/igt@i915_pm_rps@reset.html Known issues ------------ Here are the changes found in Patchwork_18072_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@drm_import_export@prime: - shard-tglb: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-tglb6/igt@drm_import_export@prime.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-tglb8/igt@drm_import_export@prime.html * igt@gem_ctx_isolation@nonpriv-switch@vecs0: - shard-iclb: [PASS][4] -> [DMESG-WARN][5] ([i915#1226]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-iclb5/igt@gem_ctx_isolation@nonpriv-switch@vecs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-iclb2/igt@gem_ctx_isolation@nonpriv-switch@vecs0.html * igt@gem_exec_balancer@bonded-early: - shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2079]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-tglb5/igt@gem_exec_balancer@bonded-early.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-tglb1/igt@gem_exec_balancer@bonded-early.html * igt@kms_big_fb@y-tiled-32bpp-rotate-180: - shard-skl: [PASS][8] -> [DMESG-WARN][9] ([i915#1982]) +11 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-skl10/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-skl8/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html * igt@kms_big_fb@y-tiled-64bpp-rotate-180: - shard-apl: [PASS][10] -> [DMESG-WARN][11] ([i915#1982]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-apl4/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-apl3/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html * igt@kms_color@pipe-a-ctm-0-75: - shard-kbl: [PASS][12] -> [DMESG-WARN][13] ([i915#93] / [i915#95]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-kbl3/igt@kms_color@pipe-a-ctm-0-75.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-kbl3/igt@kms_color@pipe-a-ctm-0-75.html * igt@kms_color@pipe-a-gamma: - shard-tglb: [PASS][14] -> [FAIL][15] ([i915#1149]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-tglb8/igt@kms_color@pipe-a-gamma.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-tglb5/igt@kms_color@pipe-a-gamma.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [PASS][16] -> [FAIL][17] ([i915#72]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-glk9/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-glk3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html * igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-ytiled: - shard-apl: [PASS][18] -> [DMESG-WARN][19] ([i915#1635] / [i915#95]) +17 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-apl1/igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-ytiled.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-apl2/igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-ytiled.html * igt@kms_flip@flip-vs-expired-vblank@c-dp1: - shard-apl: [PASS][20] -> [FAIL][21] ([i915#79]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-apl4/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-apl3/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render: - shard-tglb: [PASS][22] -> [DMESG-WARN][23] ([i915#1982]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html * igt@kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][24] -> [FAIL][25] ([i915#1188]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-skl4/igt@kms_hdr@bpc-switch-suspend.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-skl7/igt@kms_hdr@bpc-switch-suspend.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][26] -> [FAIL][27] ([fdo#108145] / [i915#265]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: - shard-iclb: [PASS][28] -> [DMESG-WARN][29] ([i915#1982]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-iclb2/igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-iclb3/igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html * igt@kms_psr@psr2_sprite_blt: - shard-iclb: [PASS][30] -> [SKIP][31] ([fdo#109441]) +1 similar issue [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-iclb6/igt@kms_psr@psr2_sprite_blt.html * igt@kms_sysfs_edid_timing: - shard-iclb: [PASS][32] -> [FAIL][33] ([IGT#2]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-iclb5/igt@kms_sysfs_edid_timing.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-iclb2/igt@kms_sysfs_edid_timing.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [PASS][34] -> [DMESG-WARN][35] ([i915#180]) +2 similar issues [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html #### Possible fixes #### * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-kbl: [DMESG-WARN][36] ([i915#180]) -> [PASS][37] +1 similar issue [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@bcs0.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@bcs0.html * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-apl: [DMESG-WARN][38] ([i915#1635] / [i915#95]) -> [PASS][39] +18 similar issues [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-apl6/igt@gem_exec_reloc@basic-many-active@rcs0.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-apl8/igt@gem_exec_reloc@basic-many-active@rcs0.html * igt@gem_exec_whisper@basic-forked-all: - shard-glk: [DMESG-WARN][40] ([i915#118] / [i915#95]) -> [PASS][41] [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-glk6/igt@gem_exec_whisper@basic-forked-all.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-glk8/igt@gem_exec_whisper@basic-forked-all.html * igt@gem_fenced_exec_thrash@too-many-fences: - shard-snb: [INCOMPLETE][42] ([i915#82]) -> [PASS][43] [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-snb1/igt@gem_fenced_exec_thrash@too-many-fences.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-snb1/igt@gem_fenced_exec_thrash@too-many-fences.html * igt@kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][44] ([i915#118] / [i915#95]) -> [PASS][45] +1 similar issue [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-glk8/igt@kms_big_fb@linear-64bpp-rotate-180.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-glk5/igt@kms_big_fb@linear-64bpp-rotate-180.html * igt@kms_big_fb@x-tiled-16bpp-rotate-0: - shard-skl: [DMESG-WARN][46] ([i915#1982]) -> [PASS][47] +5 similar issues [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-skl8/igt@kms_big_fb@x-tiled-16bpp-rotate-0.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-skl6/igt@kms_big_fb@x-tiled-16bpp-rotate-0.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-skl: [INCOMPLETE][48] ([i915#300]) -> [PASS][49] [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-skl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html * igt@kms_cursor_edge_walk@pipe-c-64x64-bottom-edge: - shard-glk: [DMESG-WARN][50] ([i915#1982]) -> [PASS][51] [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-glk1/igt@kms_cursor_edge_walk@pipe-c-64x64-bottom-edge.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-glk8/igt@kms_cursor_edge_walk@pipe-c-64x64-bottom-edge.html * igt@kms_flip@flip-vs-wf_vblank-interruptible@a-dp1: - shard-kbl: [DMESG-WARN][52] ([i915#1982]) -> [PASS][53] [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-kbl1/igt@kms_flip@flip-vs-wf_vblank-interruptible@a-dp1.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-kbl2/igt@kms_flip@flip-vs-wf_vblank-interruptible@a-dp1.html * igt@kms_flip@plain-flip-fb-recreate@c-edp1: - shard-skl: [FAIL][54] ([i915#1928]) -> [PASS][55] [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-skl6/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-skl3/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render: - shard-kbl: [DMESG-WARN][56] ([i915#93] / [i915#95]) -> [PASS][57] +1 similar issue [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu: - shard-tglb: [DMESG-WARN][58] ([i915#402]) -> [PASS][59] [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][60] ([i915#1188]) -> [PASS][61] +1 similar issue [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c: - shard-tglb: [DMESG-WARN][62] ([i915#1982]) -> [PASS][63] +1 similar issue [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-tglb3/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-tglb7/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c.html * igt@kms_psr@psr2_cursor_plane_onoff: - shard-iclb: [SKIP][64] ([fdo#109441]) -> [PASS][65] +1 similar issue [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-iclb5/igt@kms_psr@psr2_cursor_plane_onoff.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html * igt@kms_setmode@basic: - shard-kbl: [FAIL][66] ([i915#31]) -> [PASS][67] [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-kbl7/igt@kms_setmode@basic.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-kbl1/igt@kms_setmode@basic.html * igt@kms_vblank@pipe-c-query-busy-hang: - shard-apl: [DMESG-WARN][68] ([i915#1982]) -> [PASS][69] [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-apl8/igt@kms_vblank@pipe-c-query-busy-hang.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-apl6/igt@kms_vblank@pipe-c-query-busy-hang.html * igt@perf@blocking-parameterized: - shard-iclb: [FAIL][70] ([i915#1542]) -> [PASS][71] [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-iclb2/igt@perf@blocking-parameterized.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-iclb6/igt@perf@blocking-parameterized.html #### Warnings #### * igt@gem_exec_reloc@basic-spin-others@vcs0: - shard-snb: [WARN][72] ([i915#2021]) -> [WARN][73] ([i915#2036]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-snb2/igt@gem_exec_reloc@basic-spin-others@vcs0.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-snb4/igt@gem_exec_reloc@basic-spin-others@vcs0.html * igt@kms_chamelium@vga-hpd-with-enabled-mode: - shard-apl: [SKIP][74] ([fdo#109271] / [fdo#111827]) -> [SKIP][75] ([fdo#109271] / [fdo#111827] / [i915#1635]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-apl3/igt@kms_chamelium@vga-hpd-with-enabled-mode.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-apl1/igt@kms_chamelium@vga-hpd-with-enabled-mode.html * igt@kms_color@pipe-a-ctm-0-75: - shard-tglb: [FAIL][76] ([i915#1149] / [i915#315]) -> [DMESG-FAIL][77] ([i915#1149] / [i915#402]) [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-tglb5/igt@kms_color@pipe-a-ctm-0-75.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-tglb7/igt@kms_color@pipe-a-ctm-0-75.html * igt@kms_content_protection@atomic-dpms: - shard-kbl: [TIMEOUT][78] ([i915#1319] / [i915#2119]) -> [TIMEOUT][79] ([i915#1319] / [i915#1958] / [i915#2119]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-kbl2/igt@kms_content_protection@atomic-dpms.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-kbl2/igt@kms_content_protection@atomic-dpms.html * igt@kms_content_protection@srm: - shard-kbl: [TIMEOUT][80] ([i915#1319] / [i915#1958] / [i915#2119]) -> [TIMEOUT][81] ([i915#1319] / [i915#2119]) [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-kbl7/igt@kms_content_protection@srm.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-kbl1/igt@kms_content_protection@srm.html * igt@kms_flip@flip-vs-suspend@a-edp1: - shard-skl: [DMESG-WARN][82] ([i915#1982]) -> [INCOMPLETE][83] ([i915#198]) [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-skl6/igt@kms_flip@flip-vs-suspend@a-edp1.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-skl3/igt@kms_flip@flip-vs-suspend@a-edp1.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt: - shard-apl: [SKIP][84] ([fdo#109271]) -> [SKIP][85] ([fdo#109271] / [i915#1635]) +6 similar issues [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-apl3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-apl1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff: - shard-apl: [SKIP][86] ([fdo#109271] / [i915#1635]) -> [SKIP][87] ([fdo#109271]) +5 similar issues [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-apl1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-apl2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff.html * igt@kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant: - shard-apl: [DMESG-FAIL][88] ([fdo#108145] / [i915#1635] / [i915#1982] / [i915#95]) -> [DMESG-FAIL][89] ([fdo#108145] / [i915#1635] / [i915#95]) [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-apl4/igt@kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html * igt@runner@aborted: - shard-apl: ([FAIL][90], [FAIL][91], [FAIL][92]) ([i915#1610] / [i915#1635] / [i915#2110]) -> [FAIL][93] ([i915#1635] / [i915#2110]) [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-apl7/igt@runner@aborted.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-apl1/igt@runner@aborted.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-apl2/igt@runner@aborted.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-apl4/igt@runner@aborted.html - shard-tglb: [FAIL][94] ([i915#2110]) -> [FAIL][95] ([i915#1764] / [i915#2110]) [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8698/shard-tglb2/igt@runner@aborted.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/shard-tglb3/igt@runner@aborted.html [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#1764]: https://gitlab.freedesktop.org/drm/intel/issues/1764 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2021]: https://gitlab.freedesktop.org/drm/intel/issues/2021 [i915#2036]: https://gitlab.freedesktop.org/drm/intel/issues/2036 [i915#2079]: https://gitlab.freedesktop.org/drm/intel/issues/2079 [i915#2110]: https://gitlab.freedesktop.org/drm/intel/issues/2110 [i915#2119]: https://gitlab.freedesktop.org/drm/intel/issues/2119 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (10 -> 10) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8698 -> Patchwork_18072 CI-20190529: 20190529 CI_DRM_8698: a5bde2bddb64dc774e9fc1444243b8f224a31df6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5720: f35053d4b6d7bbcf6505ef67a8bd56acc7fb2eb2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18072: 1ebdc2b628a91ef273b09fa246fc66b5cc4a2fee @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18072/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-07-03 10:56 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-07-02 18:24 [Intel-gfx] [PATCH 1/2] drm/i915: Enable TPS3/4 on all platforms that support them Ville Syrjala 2020-07-02 18:24 ` [Intel-gfx] [PATCH 2/2] drm/i915: Fix the training pattern debug print Ville Syrjala 2020-07-02 19:27 ` Manasi Navare 2020-07-03 10:56 ` Ville Syrjälä 2020-07-02 19:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: Enable TPS3/4 on all platforms that support them Patchwork 2020-07-02 20:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-07-02 22:38 ` [Intel-gfx] [PATCH 1/2] " Manasi Navare 2020-07-03 1:37 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] " Patchwork
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