From: Tomasz Nowicki <tn@semihalf.com>
To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org,
gregory.clement@bootlin.com, robh+dt@kernel.org,
hannah@marvell.com
Cc: devicetree@vger.kernel.org, catalin.marinas@arm.com,
linux-kernel@vger.kernel.org, nadavh@marvell.com,
iommu@lists.linux-foundation.org, mw@semihalf.com,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 4/4] arm64: dts: marvell: add SMMU support
Date: Thu, 2 Jul 2020 22:16:33 +0200 [thread overview]
Message-ID: <20200702201633.22693-5-tn@semihalf.com> (raw)
In-Reply-To: <20200702201633.22693-1-tn@semihalf.com>
From: Marcin Wojtas <mw@semihalf.com>
Add IOMMU node for Marvell AP806 based SoCs together with platform
and PCI device Stream ID mapping.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
---
arch/arm64/boot/dts/marvell/armada-8040.dtsi | 36 +++++++++++++++++++
arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 17 +++++++++
2 files changed, 53 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-8040.dtsi b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
index 7699b19224c2..25c1df709f72 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
@@ -23,3 +23,39 @@
&cp0_rtc {
status = "disabled";
};
+
+&cp0_usb3_0 {
+ iommus = <&smmu 0x440>;
+};
+
+&cp0_usb3_1 {
+ iommus = <&smmu 0x441>;
+};
+
+&cp0_sata0 {
+ iommus = <&smmu 0x444>;
+};
+
+&cp0_sdhci0 {
+ iommus = <&smmu 0x445>;
+};
+
+&cp1_sata0 {
+ iommus = <&smmu 0x454>;
+};
+
+&cp1_usb3_0 {
+ iommus = <&smmu 0x450>;
+};
+
+&cp1_usb3_1 {
+ iommus = <&smmu 0x451>;
+};
+
+&cp0_pcie0 {
+ iommu-map =
+ <0x0 &smmu 0x480 0x20>,
+ <0x100 &smmu 0x4a0 0x20>,
+ <0x200 &smmu 0x4c0 0x20>;
+ iommu-map-mask = <0x031f>;
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
index 7f9b9a647717..ded8b8082d79 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
@@ -56,6 +56,23 @@
compatible = "simple-bus";
ranges = <0x0 0x0 0xf0000000 0x1000000>;
+ smmu: iommu@5000000 {
+ compatible = "marvell,ap806-smmu-500", "arm,mmu-500";
+ reg = <0x100000 0x100000>;
+ dma-coherent;
+ #iommu-cells = <1>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
gic: interrupt-controller@210000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.17.1
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
WARNING: multiple messages have this Message-ID (diff)
From: Tomasz Nowicki <tn@semihalf.com>
To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org,
gregory.clement@bootlin.com, robh+dt@kernel.org,
hannah@marvell.com
Cc: devicetree@vger.kernel.org, catalin.marinas@arm.com,
linux-kernel@vger.kernel.org, nadavh@marvell.com,
iommu@lists.linux-foundation.org,
Tomasz Nowicki <tn@semihalf.com>,
mw@semihalf.com, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 4/4] arm64: dts: marvell: add SMMU support
Date: Thu, 2 Jul 2020 22:16:33 +0200 [thread overview]
Message-ID: <20200702201633.22693-5-tn@semihalf.com> (raw)
In-Reply-To: <20200702201633.22693-1-tn@semihalf.com>
From: Marcin Wojtas <mw@semihalf.com>
Add IOMMU node for Marvell AP806 based SoCs together with platform
and PCI device Stream ID mapping.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
---
arch/arm64/boot/dts/marvell/armada-8040.dtsi | 36 +++++++++++++++++++
arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 17 +++++++++
2 files changed, 53 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-8040.dtsi b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
index 7699b19224c2..25c1df709f72 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
@@ -23,3 +23,39 @@
&cp0_rtc {
status = "disabled";
};
+
+&cp0_usb3_0 {
+ iommus = <&smmu 0x440>;
+};
+
+&cp0_usb3_1 {
+ iommus = <&smmu 0x441>;
+};
+
+&cp0_sata0 {
+ iommus = <&smmu 0x444>;
+};
+
+&cp0_sdhci0 {
+ iommus = <&smmu 0x445>;
+};
+
+&cp1_sata0 {
+ iommus = <&smmu 0x454>;
+};
+
+&cp1_usb3_0 {
+ iommus = <&smmu 0x450>;
+};
+
+&cp1_usb3_1 {
+ iommus = <&smmu 0x451>;
+};
+
+&cp0_pcie0 {
+ iommu-map =
+ <0x0 &smmu 0x480 0x20>,
+ <0x100 &smmu 0x4a0 0x20>,
+ <0x200 &smmu 0x4c0 0x20>;
+ iommu-map-mask = <0x031f>;
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
index 7f9b9a647717..ded8b8082d79 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
@@ -56,6 +56,23 @@
compatible = "simple-bus";
ranges = <0x0 0x0 0xf0000000 0x1000000>;
+ smmu: iommu@5000000 {
+ compatible = "marvell,ap806-smmu-500", "arm,mmu-500";
+ reg = <0x100000 0x100000>;
+ dma-coherent;
+ #iommu-cells = <1>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
gic: interrupt-controller@210000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Tomasz Nowicki <tn@semihalf.com>
To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org,
gregory.clement@bootlin.com, robh+dt@kernel.org,
hannah@marvell.com
Cc: linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org,
devicetree@vger.kernel.org, catalin.marinas@arm.com,
nadavh@marvell.com, linux-arm-kernel@lists.infradead.org,
mw@semihalf.com, Tomasz Nowicki <tn@semihalf.com>
Subject: [PATCH v3 4/4] arm64: dts: marvell: add SMMU support
Date: Thu, 2 Jul 2020 22:16:33 +0200 [thread overview]
Message-ID: <20200702201633.22693-5-tn@semihalf.com> (raw)
In-Reply-To: <20200702201633.22693-1-tn@semihalf.com>
From: Marcin Wojtas <mw@semihalf.com>
Add IOMMU node for Marvell AP806 based SoCs together with platform
and PCI device Stream ID mapping.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
---
arch/arm64/boot/dts/marvell/armada-8040.dtsi | 36 +++++++++++++++++++
arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 17 +++++++++
2 files changed, 53 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-8040.dtsi b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
index 7699b19224c2..25c1df709f72 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
@@ -23,3 +23,39 @@
&cp0_rtc {
status = "disabled";
};
+
+&cp0_usb3_0 {
+ iommus = <&smmu 0x440>;
+};
+
+&cp0_usb3_1 {
+ iommus = <&smmu 0x441>;
+};
+
+&cp0_sata0 {
+ iommus = <&smmu 0x444>;
+};
+
+&cp0_sdhci0 {
+ iommus = <&smmu 0x445>;
+};
+
+&cp1_sata0 {
+ iommus = <&smmu 0x454>;
+};
+
+&cp1_usb3_0 {
+ iommus = <&smmu 0x450>;
+};
+
+&cp1_usb3_1 {
+ iommus = <&smmu 0x451>;
+};
+
+&cp0_pcie0 {
+ iommu-map =
+ <0x0 &smmu 0x480 0x20>,
+ <0x100 &smmu 0x4a0 0x20>,
+ <0x200 &smmu 0x4c0 0x20>;
+ iommu-map-mask = <0x031f>;
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
index 7f9b9a647717..ded8b8082d79 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
@@ -56,6 +56,23 @@
compatible = "simple-bus";
ranges = <0x0 0x0 0xf0000000 0x1000000>;
+ smmu: iommu@5000000 {
+ compatible = "marvell,ap806-smmu-500", "arm,mmu-500";
+ reg = <0x100000 0x100000>;
+ dma-coherent;
+ #iommu-cells = <1>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
gic: interrupt-controller@210000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.17.1
next prev parent reply other threads:[~2020-07-02 20:42 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-02 20:16 [PATCH v3 0/4] Add system mmu support for Armada-806 Tomasz Nowicki
2020-07-02 20:16 ` Tomasz Nowicki
2020-07-02 20:16 ` Tomasz Nowicki
2020-07-02 20:16 ` [PATCH v3 1/4] iommu/arm-smmu: Add SMMU ID2 register fixup hook Tomasz Nowicki
2020-07-02 20:16 ` Tomasz Nowicki
2020-07-02 20:16 ` Tomasz Nowicki
2020-07-03 8:24 ` Robin Murphy
2020-07-03 8:24 ` Robin Murphy
2020-07-03 8:24 ` Robin Murphy
2020-07-03 9:19 ` Tomasz Nowicki
2020-07-03 9:19 ` Tomasz Nowicki
2020-07-03 9:19 ` Tomasz Nowicki
2020-07-02 20:16 ` [PATCH v3 2/4] iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum #582743 Tomasz Nowicki
2020-07-02 20:16 ` Tomasz Nowicki
2020-07-02 20:16 ` Tomasz Nowicki
2020-07-03 9:03 ` Robin Murphy
2020-07-03 9:03 ` Robin Murphy
2020-07-03 9:03 ` Robin Murphy
2020-07-03 11:24 ` Tomasz Nowicki
2020-07-03 11:24 ` Tomasz Nowicki
2020-07-03 11:24 ` Tomasz Nowicki
2020-07-02 20:16 ` [PATCH v3 3/4] dt-bindings: arm-smmu: add compatible string for Marvell Armada-AP806 SMMU-500 Tomasz Nowicki
2020-07-02 20:16 ` Tomasz Nowicki
2020-07-02 20:16 ` Tomasz Nowicki
2020-07-03 9:05 ` Robin Murphy
2020-07-03 9:05 ` Robin Murphy
2020-07-03 9:05 ` Robin Murphy
2020-07-03 9:26 ` Tomasz Nowicki
2020-07-03 9:26 ` Tomasz Nowicki
2020-07-03 9:26 ` Tomasz Nowicki
2020-07-13 21:36 ` Rob Herring
2020-07-13 21:36 ` Rob Herring
2020-07-13 21:36 ` Rob Herring
2020-07-02 20:16 ` Tomasz Nowicki [this message]
2020-07-02 20:16 ` [PATCH v3 4/4] arm64: dts: marvell: add SMMU support Tomasz Nowicki
2020-07-02 20:16 ` Tomasz Nowicki
2020-07-03 9:16 ` Robin Murphy
2020-07-03 9:16 ` Robin Murphy
2020-07-03 9:16 ` Robin Murphy
2020-07-03 9:33 ` Tomasz Nowicki
2020-07-03 9:33 ` Tomasz Nowicki
2020-07-03 9:33 ` Tomasz Nowicki
2020-07-03 10:38 ` Marcin Wojtas
2020-07-03 10:38 ` Marcin Wojtas
2020-07-03 10:38 ` Marcin Wojtas
2020-07-14 8:19 ` [PATCH v3 0/4] Add system mmu support for Armada-806 Will Deacon
2020-07-14 8:19 ` Will Deacon
2020-07-14 8:19 ` Will Deacon
2020-07-14 10:26 ` Tomasz Nowicki
2020-07-14 10:26 ` Tomasz Nowicki
2020-07-14 10:26 ` Tomasz Nowicki
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