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From: kernel test robot <lkp@intel.com>
To: Lucas De Marchi <lucas.demarchi@intel.com>,
	intel-gfx@lists.freedesktop.org
Cc: clang-built-linux@googlegroups.com, kbuild-all@lists.01.org
Subject: Re: [Intel-gfx] [PATCH v3 03/28] drm/i915/dg1: Add DG1 PCI IDs
Date: Thu, 2 Jul 2020 20:37:16 +0800	[thread overview]
Message-ID: <202007022017.086ppwct%lkp@intel.com> (raw)
In-Reply-To: <20200701235339.32608-4-lucas.demarchi@intel.com>

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Hi Lucas,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20200702]
[cannot apply to v5.8-rc3]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use  as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Lucas-De-Marchi/Introduce-DG1/20200702-075819
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-r025-20200702 (attached as .config)
compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project 003a086ffc0d1affbb8300b36225fb8150a2d40a)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install x86_64 cross compiling tool for clang build
        # apt-get install binutils-x86-64-linux-gnu
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/i915_pci.c:903:39: warning: unused variable 'dg1_info' [-Wunused-const-variable]
   static const struct intel_device_info dg1_info = {
                                         ^
   1 warning generated.

vim +/dg1_info +903 drivers/gpu/drm/i915/i915_pci.c

   896	
   897	#define GEN12_DGFX_FEATURES \
   898		GEN12_FEATURES, \
   899		.memory_regions = REGION_SMEM | REGION_LMEM, \
   900		.has_master_unit_irq = 1, \
   901		.is_dgfx = 1
   902	
 > 903	static const struct intel_device_info dg1_info = {
   904		GEN12_DGFX_FEATURES,
   905		PLATFORM(INTEL_DG1),
   906		.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
   907		.require_force_probe = 1,
   908		.engine_mask =
   909			BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
   910			BIT(VCS0) | BIT(VCS2),
   911	};
   912	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: kernel test robot <lkp@intel.com>
To: kbuild-all@lists.01.org
Subject: Re: [Intel-gfx] [PATCH v3 03/28] drm/i915/dg1: Add DG1 PCI IDs
Date: Thu, 02 Jul 2020 20:37:16 +0800	[thread overview]
Message-ID: <202007022017.086ppwct%lkp@intel.com> (raw)
In-Reply-To: <20200701235339.32608-4-lucas.demarchi@intel.com>

[-- Attachment #1: Type: text/plain, Size: 2280 bytes --]

Hi Lucas,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20200702]
[cannot apply to v5.8-rc3]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use  as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Lucas-De-Marchi/Introduce-DG1/20200702-075819
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-r025-20200702 (attached as .config)
compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project 003a086ffc0d1affbb8300b36225fb8150a2d40a)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install x86_64 cross compiling tool for clang build
        # apt-get install binutils-x86-64-linux-gnu
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/i915_pci.c:903:39: warning: unused variable 'dg1_info' [-Wunused-const-variable]
   static const struct intel_device_info dg1_info = {
                                         ^
   1 warning generated.

vim +/dg1_info +903 drivers/gpu/drm/i915/i915_pci.c

   896	
   897	#define GEN12_DGFX_FEATURES \
   898		GEN12_FEATURES, \
   899		.memory_regions = REGION_SMEM | REGION_LMEM, \
   900		.has_master_unit_irq = 1, \
   901		.is_dgfx = 1
   902	
 > 903	static const struct intel_device_info dg1_info = {
   904		GEN12_DGFX_FEATURES,
   905		PLATFORM(INTEL_DG1),
   906		.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
   907		.require_force_probe = 1,
   908		.engine_mask =
   909			BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
   910			BIT(VCS0) | BIT(VCS2),
   911	};
   912	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

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  parent reply	other threads:[~2020-07-02 12:38 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 01/28] drm/i915: Add has_master_unit_irq flag Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 02/28] drm/i915/dg1: add initial DG-1 definitions Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 03/28] drm/i915/dg1: Add DG1 PCI IDs Lucas De Marchi
2020-07-02  6:00   ` kernel test robot
2020-07-02  6:00     ` kernel test robot
2020-07-09 20:01     ` Lucas De Marchi
2020-07-09 20:56       ` Lucas De Marchi
2020-07-02 12:37   ` kernel test robot [this message]
2020-07-02 12:37     ` kernel test robot
2020-07-08 17:08   ` Daniel Vetter
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 04/28] drm/i915/dg1: add support for the master unit interrupt Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 05/28] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 06/28] drm/i915/dg1: Add fake PCH Lucas De Marchi
2020-07-08  7:28   ` Srivatsa, Anusha
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 07/28] drm/i915/dg1: Initialize RAWCLK properly Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 08/28] drm/i915/dg1: Define MOCS table for DG1 Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 09/28] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 10/28] drm/i915/dg1: Increase mmio size to 4MB Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 11/28] drm/i915/dg1: Wait for pcode/uncore handshake at startup Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 12/28] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 13/28] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 14/28] drm/i915/dg1: Enable DPLL " Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 15/28] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 16/28] drm/i915/dg1: invert HPD pins Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 17/28] drm/i915/dg1: gmbus pin mapping Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 18/28] drm/i915/dg1: Enable first 2 ports for DG1 Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 19/28] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Lucas De Marchi
2020-07-08  7:17   ` Srivatsa, Anusha
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 20/28] drm/i915/dg1: Update comp master/slave relationships for PHYs Lucas De Marchi
2020-07-08  7:51   ` Srivatsa, Anusha
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 21/28] drm/i915/dg1: Update voltage swing tables for DP Lucas De Marchi
2020-07-08 10:23   ` Srivatsa, Anusha
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 22/28] drm/i915/dg1: provide port/phy mapping for vbt Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 23/28] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 24/28] drm/i915/dg1: enable PORT C/D aka D/E Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 25/28] drm/i915/dg1: Load DMC Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 26/28] drm/i915/rkl: Add initial workarounds Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 27/28] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 28/28] drm/i915/dg1: DG1 does not support DC6 Lucas De Marchi
2020-07-02  0:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 (rev3) Patchwork
2020-07-02  0:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-07-02  0:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-02  4:44 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-07-02  7:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 (rev4) Patchwork
2020-07-02  7:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-07-02  8:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-02 11:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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