Re: [PATCH 6/7] arm64: dts: keembay: Add device tree for Keem Bay SoC

From: Sudeep Holla <sudeep.holla@arm.com>
To: Daniele Alessandrelli <daniele.alessandrelli@linux.intel.com>
Cc: devicetree@vger.kernel.org, Arnd Bergmann <arnd@arndb.de>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Jassi Brar <jassisinghbrar@gmail.com>,
	linux-kernel@vger.kernel.org, Dinh Nguyen <dinguyen@kernel.org>,
	Rob Herring <robh+dt@kernel.org>, Olof Johansson <olof@lixom.net>,
	Paul Murphy <paul.j.murphy@intel.com>,
	Will Deacon <will@kernel.org>,
	Daniele Alessandrelli <daniele.alessandrelli@intel.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 6/7] arm64: dts: keembay: Add device tree for Keem Bay SoC
Date: Wed, 8 Jul 2020 21:39:13 +0100	[thread overview]
Message-ID: <20200708203913.GC31671@bogus> (raw)
In-Reply-To: <20200616155613.121242-7-daniele.alessandrelli@linux.intel.com>

On Tue, Jun 16, 2020 at 04:56:12PM +0100, Daniele Alessandrelli wrote:
> From: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
> 
> Add initial device tree for Intel Movidius SoC code-named Keem Bay.
> 
> This initial DT includes nodes for Cortex-A53 cores, UARTs, timers, GIC,
> PSCI, PMU, and Keem Bay SCMI mailbox.
> 
> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
> Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
> ---
>  MAINTAINERS                                |   1 +
>  arch/arm64/boot/dts/intel/keembay-soc.dtsi | 172 +++++++++++++++++++++
>  2 files changed, 173 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/intel/keembay-soc.dtsi
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 3b919aa8b1bd..610907bf391b 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1959,6 +1959,7 @@ M:	Paul J. Murphy <paul.j.murphy@intel.com>
>  M:	Daniele Alessandrelli <daniele.alessandrelli@intel.com>
>  S:	Maintained
>  F:	Documentation/devicetree/bindings/arm/keembay.yaml
> +F:	arch/arm64/boot/dts/intel/keembay-soc.dtsi
>  F:	include/dt-bindings/clock/keembay-clocks.h
>  F:	include/dt-bindings/power/keembay-power.h
>  
> diff --git a/arch/arm64/boot/dts/intel/keembay-soc.dtsi b/arch/arm64/boot/dts/intel/keembay-soc.dtsi
> new file mode 100644
> index 000000000000..bd0a48f24e09
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/keembay-soc.dtsi
> @@ -0,0 +1,172 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2020, Intel Corporation.
> + *
> + * Device tree describing Keem Bay SoC.
> + */
> +
> +#include <dt-bindings/clock/keembay-clocks.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/power/keembay-power.h>
> +
> +/ {
> +	compatible = "intel,keembay";
> +	interrupt-parent = <&gic>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x0>;
> +			enable-method = "psci";
> +			clocks = <&scmi_dvfs 0>;
> +		};
> +
> +		cpu@1 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x1>;
> +			enable-method = "psci";
> +			clocks = <&scmi_dvfs 0>;
> +		};
> +
> +		cpu@2 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x2>;
> +			enable-method = "psci";
> +			clocks = <&scmi_dvfs 0>;
> +		};
> +
> +		cpu@3 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x3>;
> +			enable-method = "psci";
> +			clocks = <&scmi_dvfs 0>;
> +		};
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-0.2";
> +		method = "smc";
> +	};
> +
> +	firmware: firmware {
> +
> +		scmi: scmi {
> +			compatible = "arm,scmi";

The above must be changed to "arm,scmi-smc".
Add "arm,smc-id = <sip_id_for_this>" and drop mboxes.

-- 
Regards,
Sudeep

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