From: Rob Herring <robh@kernel.org>
To: Krishna Reddy <vdumpa@nvidia.com>
Cc: snikam@nvidia.com, devicetree@vger.kernel.org,
nicoleotsuka@gmail.com, mperttunen@nvidia.com,
praithatha@nvidia.com, bhuntsman@nvidia.com, will@kernel.org,
linux-kernel@vger.kernel.org, jonathanh@nvidia.com,
talho@nvidia.com, iommu@lists.linux-foundation.org,
nicolinc@nvidia.com, linux-tegra@vger.kernel.org,
yhsu@nvidia.com, treding@nvidia.com, robin.murphy@arm.com,
linux-arm-kernel@lists.infradead.org, bbiswas@nvidia.com
Subject: Re: [PATCH v10 4/5] dt-bindings: arm-smmu: add binding for Tegra194 SMMU
Date: Thu, 9 Jul 2020 14:13:48 -0600 [thread overview]
Message-ID: <20200709201348.GA808454@bogus> (raw)
In-Reply-To: <20200708050017.31563-5-vdumpa@nvidia.com>
On Tue, Jul 07, 2020 at 10:00:16PM -0700, Krishna Reddy wrote:
> Add binding for NVIDIA's Tegra194 SoC SMMU.
>
> Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
> ---
> .../devicetree/bindings/iommu/arm,smmu.yaml | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> index d7ceb4c34423..ac1f526c3424 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> @@ -38,6 +38,11 @@ properties:
> - qcom,sc7180-smmu-500
> - qcom,sdm845-smmu-500
> - const: arm,mmu-500
> + - description: NVIDIA SoCs that program two ARM MMU-500s identically
> + items:
> + - enum:
> + - nvidia,tegra194-smmu
> + - const: nvidia,smmu-500
> - items:
> - const: arm,mmu-500
> - const: arm,smmu-v2
> @@ -138,6 +143,19 @@ required:
>
> additionalProperties: false
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - nvidia,tegra194-smmu
> + then:
> + properties:
> + reg:
> + minItems: 2
> + maxItems: 2
This doesn't work. The main part of the schema already said there's only
1 reg region. This part is ANDed with that, not an override. You need to
add an else clause with 'maxItems: 1' and change the base schema to
{minItems: 1, maxItems: 2}.
Rob
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
To: Krishna Reddy <vdumpa-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org,
will-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
robin.murphy-5wv7dgnIgG8@public.gmane.org,
treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
yhsu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
snikam-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
praithatha-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
talho-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
bbiswas-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
nicolinc-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
bhuntsman-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
nicoleotsuka-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
Subject: Re: [PATCH v10 4/5] dt-bindings: arm-smmu: add binding for Tegra194 SMMU
Date: Thu, 9 Jul 2020 14:13:48 -0600 [thread overview]
Message-ID: <20200709201348.GA808454@bogus> (raw)
In-Reply-To: <20200708050017.31563-5-vdumpa-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On Tue, Jul 07, 2020 at 10:00:16PM -0700, Krishna Reddy wrote:
> Add binding for NVIDIA's Tegra194 SoC SMMU.
>
> Signed-off-by: Krishna Reddy <vdumpa-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> .../devicetree/bindings/iommu/arm,smmu.yaml | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> index d7ceb4c34423..ac1f526c3424 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> @@ -38,6 +38,11 @@ properties:
> - qcom,sc7180-smmu-500
> - qcom,sdm845-smmu-500
> - const: arm,mmu-500
> + - description: NVIDIA SoCs that program two ARM MMU-500s identically
> + items:
> + - enum:
> + - nvidia,tegra194-smmu
> + - const: nvidia,smmu-500
> - items:
> - const: arm,mmu-500
> - const: arm,smmu-v2
> @@ -138,6 +143,19 @@ required:
>
> additionalProperties: false
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - nvidia,tegra194-smmu
> + then:
> + properties:
> + reg:
> + minItems: 2
> + maxItems: 2
This doesn't work. The main part of the schema already said there's only
1 reg region. This part is ANDed with that, not an override. You need to
add an else clause with 'maxItems: 1' and change the base schema to
{minItems: 1, maxItems: 2}.
Rob
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Krishna Reddy <vdumpa@nvidia.com>
Cc: snikam@nvidia.com, devicetree@vger.kernel.org,
nicoleotsuka@gmail.com, mperttunen@nvidia.com,
praithatha@nvidia.com, bhuntsman@nvidia.com, will@kernel.org,
joro@8bytes.org, linux-kernel@vger.kernel.org,
jonathanh@nvidia.com, talho@nvidia.com,
iommu@lists.linux-foundation.org, nicolinc@nvidia.com,
linux-tegra@vger.kernel.org, yhsu@nvidia.com, treding@nvidia.com,
robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org,
bbiswas@nvidia.com
Subject: Re: [PATCH v10 4/5] dt-bindings: arm-smmu: add binding for Tegra194 SMMU
Date: Thu, 9 Jul 2020 14:13:48 -0600 [thread overview]
Message-ID: <20200709201348.GA808454@bogus> (raw)
In-Reply-To: <20200708050017.31563-5-vdumpa@nvidia.com>
On Tue, Jul 07, 2020 at 10:00:16PM -0700, Krishna Reddy wrote:
> Add binding for NVIDIA's Tegra194 SoC SMMU.
>
> Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
> ---
> .../devicetree/bindings/iommu/arm,smmu.yaml | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> index d7ceb4c34423..ac1f526c3424 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> @@ -38,6 +38,11 @@ properties:
> - qcom,sc7180-smmu-500
> - qcom,sdm845-smmu-500
> - const: arm,mmu-500
> + - description: NVIDIA SoCs that program two ARM MMU-500s identically
> + items:
> + - enum:
> + - nvidia,tegra194-smmu
> + - const: nvidia,smmu-500
> - items:
> - const: arm,mmu-500
> - const: arm,smmu-v2
> @@ -138,6 +143,19 @@ required:
>
> additionalProperties: false
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - nvidia,tegra194-smmu
> + then:
> + properties:
> + reg:
> + minItems: 2
> + maxItems: 2
This doesn't work. The main part of the schema already said there's only
1 reg region. This part is ANDed with that, not an override. You need to
add an else clause with 'maxItems: 1' and change the base schema to
{minItems: 1, maxItems: 2}.
Rob
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Krishna Reddy <vdumpa@nvidia.com>
Cc: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com,
treding@nvidia.com, jonathanh@nvidia.com,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org,
linux-tegra@vger.kernel.org, yhsu@nvidia.com, snikam@nvidia.com,
praithatha@nvidia.com, talho@nvidia.com, bbiswas@nvidia.com,
mperttunen@nvidia.com, nicolinc@nvidia.com, bhuntsman@nvidia.com,
nicoleotsuka@gmail.com
Subject: Re: [PATCH v10 4/5] dt-bindings: arm-smmu: add binding for Tegra194 SMMU
Date: Thu, 9 Jul 2020 14:13:48 -0600 [thread overview]
Message-ID: <20200709201348.GA808454@bogus> (raw)
In-Reply-To: <20200708050017.31563-5-vdumpa@nvidia.com>
On Tue, Jul 07, 2020 at 10:00:16PM -0700, Krishna Reddy wrote:
> Add binding for NVIDIA's Tegra194 SoC SMMU.
>
> Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
> ---
> .../devicetree/bindings/iommu/arm,smmu.yaml | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> index d7ceb4c34423..ac1f526c3424 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> @@ -38,6 +38,11 @@ properties:
> - qcom,sc7180-smmu-500
> - qcom,sdm845-smmu-500
> - const: arm,mmu-500
> + - description: NVIDIA SoCs that program two ARM MMU-500s identically
> + items:
> + - enum:
> + - nvidia,tegra194-smmu
> + - const: nvidia,smmu-500
> - items:
> - const: arm,mmu-500
> - const: arm,smmu-v2
> @@ -138,6 +143,19 @@ required:
>
> additionalProperties: false
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - nvidia,tegra194-smmu
> + then:
> + properties:
> + reg:
> + minItems: 2
> + maxItems: 2
This doesn't work. The main part of the schema already said there's only
1 reg region. This part is ANDed with that, not an override. You need to
add an else clause with 'maxItems: 1' and change the base schema to
{minItems: 1, maxItems: 2}.
Rob
next prev parent reply other threads:[~2020-07-09 20:13 UTC|newest]
Thread overview: 100+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-08 5:00 [PATCH v10 0/5] NVIDIA ARM SMMU Implementation Krishna Reddy
2020-07-08 5:00 ` Krishna Reddy
2020-07-08 5:00 ` Krishna Reddy
2020-07-08 5:00 ` Krishna Reddy
2020-07-08 5:00 ` [PATCH v10 1/5] iommu/arm-smmu: move TLB timeout and spin count macros Krishna Reddy
2020-07-08 5:00 ` Krishna Reddy
2020-07-08 5:00 ` Krishna Reddy
2020-07-08 5:00 ` Krishna Reddy
2020-07-08 12:05 ` Jon Hunter
2020-07-08 12:05 ` Jon Hunter
2020-07-08 12:05 ` Jon Hunter
2020-07-08 12:05 ` Jon Hunter
2020-07-08 20:37 ` Nicolin Chen
2020-07-08 20:37 ` Nicolin Chen
2020-07-08 20:37 ` Nicolin Chen
2020-07-08 20:37 ` Nicolin Chen
2020-07-08 5:00 ` [PATCH v10 2/5] iommu/arm-smmu: ioremap smmu mmio region before implementation init Krishna Reddy
2020-07-08 5:00 ` Krishna Reddy
2020-07-08 5:00 ` Krishna Reddy
2020-07-08 5:00 ` Krishna Reddy
2020-07-08 12:05 ` Jon Hunter
2020-07-08 12:05 ` Jon Hunter
2020-07-08 12:05 ` Jon Hunter
2020-07-08 12:05 ` Jon Hunter
2020-07-08 20:37 ` Nicolin Chen
2020-07-08 20:37 ` Nicolin Chen
2020-07-08 20:37 ` Nicolin Chen
2020-07-08 20:37 ` Nicolin Chen
2020-07-13 14:02 ` Robin Murphy
2020-07-13 14:02 ` Robin Murphy
2020-07-13 14:02 ` Robin Murphy
2020-07-13 14:02 ` Robin Murphy
2020-07-08 5:00 ` [PATCH v10 3/5] iommu/arm-smmu: add NVIDIA implementation for ARM MMU-500 usage Krishna Reddy
2020-07-08 5:00 ` Krishna Reddy
2020-07-08 5:00 ` Krishna Reddy
2020-07-08 5:00 ` Krishna Reddy
2020-07-08 12:24 ` Jon Hunter
2020-07-08 12:24 ` Jon Hunter
2020-07-08 12:24 ` Jon Hunter
2020-07-08 12:24 ` Jon Hunter
2020-07-08 20:36 ` Nicolin Chen
2020-07-08 20:36 ` Nicolin Chen
2020-07-08 20:36 ` Nicolin Chen
2020-07-08 20:36 ` Nicolin Chen
2020-07-08 5:00 ` [PATCH v10 4/5] dt-bindings: arm-smmu: add binding for Tegra194 SMMU Krishna Reddy
2020-07-08 5:00 ` Krishna Reddy
2020-07-08 5:00 ` Krishna Reddy
2020-07-08 5:00 ` Krishna Reddy
2020-07-08 12:25 ` Jon Hunter
2020-07-08 12:25 ` Jon Hunter
2020-07-08 12:25 ` Jon Hunter
2020-07-08 12:25 ` Jon Hunter
2020-07-09 20:13 ` Rob Herring [this message]
2020-07-09 20:13 ` Rob Herring
2020-07-09 20:13 ` Rob Herring
2020-07-09 20:13 ` Rob Herring
2020-07-10 20:29 ` Krishna Reddy
2020-07-10 20:29 ` Krishna Reddy
2020-07-10 20:29 ` Krishna Reddy
2020-07-10 20:29 ` Krishna Reddy
2020-07-13 14:10 ` Robin Murphy
2020-07-13 14:10 ` Robin Murphy
2020-07-13 14:10 ` Robin Murphy
2020-07-13 14:10 ` Robin Murphy
2020-07-14 14:22 ` Rob Herring
2020-07-14 14:22 ` Rob Herring
2020-07-14 14:22 ` Rob Herring
2020-07-14 14:22 ` Rob Herring
2020-07-08 5:00 ` [PATCH v10 5/5] iommu/arm-smmu: Add global/context fault implementation hooks Krishna Reddy
2020-07-08 5:00 ` Krishna Reddy
2020-07-08 5:00 ` Krishna Reddy
2020-07-08 5:00 ` Krishna Reddy
2020-07-08 12:28 ` Jon Hunter
2020-07-08 12:28 ` Jon Hunter
2020-07-08 12:28 ` Jon Hunter
2020-07-08 12:28 ` Jon Hunter
2020-07-08 20:36 ` Nicolin Chen
2020-07-08 20:36 ` Nicolin Chen
2020-07-08 20:36 ` Nicolin Chen
2020-07-08 20:36 ` Nicolin Chen
2020-07-13 13:44 ` Will Deacon
2020-07-13 13:44 ` Will Deacon
2020-07-13 13:44 ` Will Deacon
2020-07-13 13:44 ` Will Deacon
2020-07-17 11:58 ` Robin Murphy
2020-07-17 11:58 ` Robin Murphy
2020-07-17 11:58 ` Robin Murphy
2020-07-17 11:58 ` Robin Murphy
2020-07-13 13:50 ` [PATCH v10 0/5] NVIDIA ARM SMMU Implementation Will Deacon
2020-07-13 13:50 ` Will Deacon
2020-07-13 13:50 ` Will Deacon
2020-07-13 13:50 ` Will Deacon
2020-07-17 10:03 ` Will Deacon
2020-07-17 10:03 ` Will Deacon
2020-07-17 10:03 ` Will Deacon
2020-07-17 10:03 ` Will Deacon
2020-07-17 22:36 ` Krishna Reddy
2020-07-17 22:36 ` Krishna Reddy
2020-07-17 22:36 ` Krishna Reddy
2020-07-17 22:36 ` Krishna Reddy
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