From: Joerg Roedel <joro@8bytes.org>
To: Robin Murphy <robin.murphy@arm.com>
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
iommu@lists.linux-foundation.org, jonathan.lemon@gmail.com,
dwmw2@infradead.org, hch@lst.de,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/2] iommu/intel: Avoid SAC address trick for PCIe devices
Date: Fri, 10 Jul 2020 16:20:37 +0200 [thread overview]
Message-ID: <20200710142037.GM27672@8bytes.org> (raw)
In-Reply-To: <e583fc6dd1fb4ffc90310ff4372ee776f9cc7a3c.1594207679.git.robin.murphy@arm.com>
On Wed, Jul 08, 2020 at 12:32:41PM +0100, Robin Murphy wrote:
> For devices stuck behind a conventional PCI bus, saving extra cycles at
> 33MHz is probably fairly significant. However since native PCI Express
> is now the norm for high-performance devices, the optimisation to always
> prefer 32-bit addresses for the sake of avoiding DAC is starting to look
> rather anachronistic. Technically 32-bit addresses do have shorter TLPs
> on PCIe, but unless the device is saturating its link bandwidth with
> small transfers it seems unlikely that the difference is appreciable.
>
> What definitely is appreciable, however, is that the IOVA allocator
> doesn't behave all that well once the 32-bit space starts getting full.
> As DMA working sets get bigger, this optimisation increasingly backfires
> and adds considerable overhead to the dma_map path for use-cases like
> high-bandwidth networking.
>
> As such, let's simply take it out of consideration for PCIe devices.
> Technically this might work out suboptimal for a PCIe device stuck
> behind a conventional PCI bridge, or for PCI-X devices that also have
> native 64-bit addressing, but neither of those are likely to be found
> in performance-critical parts of modern systems.
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
> drivers/iommu/intel/iommu.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Applied both, thanks.
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
WARNING: multiple messages have this Message-ID (diff)
From: Joerg Roedel <joro@8bytes.org>
To: Robin Murphy <robin.murphy@arm.com>
Cc: hch@lst.de, iommu@lists.linux-foundation.org,
jonathan.lemon@gmail.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, baolu.lu@linux.intel.com,
dwmw2@infradead.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/2] iommu/intel: Avoid SAC address trick for PCIe devices
Date: Fri, 10 Jul 2020 16:20:37 +0200 [thread overview]
Message-ID: <20200710142037.GM27672@8bytes.org> (raw)
In-Reply-To: <e583fc6dd1fb4ffc90310ff4372ee776f9cc7a3c.1594207679.git.robin.murphy@arm.com>
On Wed, Jul 08, 2020 at 12:32:41PM +0100, Robin Murphy wrote:
> For devices stuck behind a conventional PCI bus, saving extra cycles at
> 33MHz is probably fairly significant. However since native PCI Express
> is now the norm for high-performance devices, the optimisation to always
> prefer 32-bit addresses for the sake of avoiding DAC is starting to look
> rather anachronistic. Technically 32-bit addresses do have shorter TLPs
> on PCIe, but unless the device is saturating its link bandwidth with
> small transfers it seems unlikely that the difference is appreciable.
>
> What definitely is appreciable, however, is that the IOVA allocator
> doesn't behave all that well once the 32-bit space starts getting full.
> As DMA working sets get bigger, this optimisation increasingly backfires
> and adds considerable overhead to the dma_map path for use-cases like
> high-bandwidth networking.
>
> As such, let's simply take it out of consideration for PCIe devices.
> Technically this might work out suboptimal for a PCIe device stuck
> behind a conventional PCI bridge, or for PCI-X devices that also have
> native 64-bit addressing, but neither of those are likely to be found
> in performance-critical parts of modern systems.
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
> drivers/iommu/intel/iommu.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Applied both, thanks.
WARNING: multiple messages have this Message-ID (diff)
From: Joerg Roedel <joro@8bytes.org>
To: Robin Murphy <robin.murphy@arm.com>
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
iommu@lists.linux-foundation.org, jonathan.lemon@gmail.com,
dwmw2@infradead.org, hch@lst.de,
linux-arm-kernel@lists.infradead.org, baolu.lu@linux.intel.com
Subject: Re: [PATCH 1/2] iommu/intel: Avoid SAC address trick for PCIe devices
Date: Fri, 10 Jul 2020 16:20:37 +0200 [thread overview]
Message-ID: <20200710142037.GM27672@8bytes.org> (raw)
In-Reply-To: <e583fc6dd1fb4ffc90310ff4372ee776f9cc7a3c.1594207679.git.robin.murphy@arm.com>
On Wed, Jul 08, 2020 at 12:32:41PM +0100, Robin Murphy wrote:
> For devices stuck behind a conventional PCI bus, saving extra cycles at
> 33MHz is probably fairly significant. However since native PCI Express
> is now the norm for high-performance devices, the optimisation to always
> prefer 32-bit addresses for the sake of avoiding DAC is starting to look
> rather anachronistic. Technically 32-bit addresses do have shorter TLPs
> on PCIe, but unless the device is saturating its link bandwidth with
> small transfers it seems unlikely that the difference is appreciable.
>
> What definitely is appreciable, however, is that the IOVA allocator
> doesn't behave all that well once the 32-bit space starts getting full.
> As DMA working sets get bigger, this optimisation increasingly backfires
> and adds considerable overhead to the dma_map path for use-cases like
> high-bandwidth networking.
>
> As such, let's simply take it out of consideration for PCIe devices.
> Technically this might work out suboptimal for a PCIe device stuck
> behind a conventional PCI bridge, or for PCI-X devices that also have
> native 64-bit addressing, but neither of those are likely to be found
> in performance-critical parts of modern systems.
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
> drivers/iommu/intel/iommu.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Applied both, thanks.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-07-10 14:20 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-08 11:32 [PATCH 1/2] iommu/intel: Avoid SAC address trick for PCIe devices Robin Murphy
2020-07-08 11:32 ` Robin Murphy
2020-07-08 11:32 ` Robin Murphy
2020-07-08 11:32 ` [PATCH 2/2] iommu/dma: " Robin Murphy
2020-07-08 11:32 ` Robin Murphy
2020-07-08 11:32 ` Robin Murphy
2020-07-13 13:14 ` Joerg Roedel
2020-07-13 13:14 ` Joerg Roedel
2020-07-13 13:14 ` Joerg Roedel
2020-07-14 11:42 ` Robin Murphy
2020-07-14 11:42 ` Robin Murphy
2020-07-14 11:42 ` Robin Murphy
2020-07-22 12:48 ` Joerg Roedel
2020-07-22 12:48 ` Joerg Roedel
2020-07-22 12:48 ` Joerg Roedel
2020-07-08 12:26 ` [PATCH 1/2] iommu/intel: " Christoph Hellwig
2020-07-08 12:26 ` Christoph Hellwig
2020-07-08 12:26 ` Christoph Hellwig
2020-07-10 14:20 ` Joerg Roedel [this message]
2020-07-10 14:20 ` Joerg Roedel
2020-07-10 14:20 ` Joerg Roedel
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