From: Jim Quinlan <james.quinlan@broadcom.com>
To: linux-pci@vger.kernel.org,
Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
Christoph Hellwig <hch@lst.de>,
bcm-kernel-feedback-list@broadcom.com,
james.quinlan@broadcom.com
Cc: Jim Quinlan <james.quinlan@broadcom.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Rob Herring <robh@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Florian Fainelli <f.fainelli@gmail.com>,
linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM
BCM2711/BCM2835 ARM ARCHITECTURE),
linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM
BCM2711/BCM2835 ARM ARCHITECTURE),
linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v8 05/12] PCI: brcmstb: Add suspend and resume pm_ops
Date: Wed, 15 Jul 2020 10:35:08 -0400 [thread overview]
Message-ID: <20200715143530.9702-6-james.quinlan@broadcom.com> (raw)
In-Reply-To: <20200715143530.9702-1-james.quinlan@broadcom.com>
From: Jim Quinlan <jquinlan@broadcom.com>
Broadcom Set-top (BrcmSTB) boards typically support S2, S3, and S5 suspend
and resume. Now the PCIe driver may do so as well.
Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
drivers/pci/controller/pcie-brcmstb.c | 47 +++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index b7a222fde3c4..7c148eb65170 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -979,6 +979,47 @@ static void brcm_pcie_turn_off(struct brcm_pcie *pcie)
brcm_pcie_bridge_sw_init_set(pcie, 1);
}
+static int brcm_pcie_suspend(struct device *dev)
+{
+ struct brcm_pcie *pcie = dev_get_drvdata(dev);
+
+ brcm_pcie_turn_off(pcie);
+ clk_disable_unprepare(pcie->clk);
+
+ return 0;
+}
+
+static int brcm_pcie_resume(struct device *dev)
+{
+ struct brcm_pcie *pcie = dev_get_drvdata(dev);
+ void __iomem *base;
+ u32 tmp;
+ int ret;
+
+ base = pcie->base;
+ clk_prepare_enable(pcie->clk);
+
+ /* Take bridge out of reset so we can access the SERDES reg */
+ brcm_pcie_bridge_sw_init_set(pcie, 0);
+
+ /* SERDES_IDDQ = 0 */
+ tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
+ u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
+ writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
+
+ /* wait for serdes to be stable */
+ udelay(100);
+
+ ret = brcm_pcie_setup(pcie);
+ if (ret)
+ return ret;
+
+ if (pcie->msi)
+ brcm_msi_set_regs(pcie->msi);
+
+ return 0;
+}
+
static void __brcm_pcie_remove(struct brcm_pcie *pcie)
{
brcm_msi_remove(pcie);
@@ -1110,12 +1151,18 @@ static int brcm_pcie_probe(struct platform_device *pdev)
MODULE_DEVICE_TABLE(of, brcm_pcie_match);
+static const struct dev_pm_ops brcm_pcie_pm_ops = {
+ .suspend_noirq = brcm_pcie_suspend,
+ .resume_noirq = brcm_pcie_resume,
+};
+
static struct platform_driver brcm_pcie_driver = {
.probe = brcm_pcie_probe,
.remove = brcm_pcie_remove,
.driver = {
.name = "brcm-pcie",
.of_match_table = brcm_pcie_match,
+ .pm = &brcm_pcie_pm_ops,
},
};
module_platform_driver(brcm_pcie_driver);
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Jim Quinlan <james.quinlan@broadcom.com>
To: linux-pci@vger.kernel.org,
Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
Christoph Hellwig <hch@lst.de>,
bcm-kernel-feedback-list@broadcom.com,
james.quinlan@broadcom.com
Cc: Rob Herring <robh@kernel.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
open list <linux-kernel@vger.kernel.org>,
Florian Fainelli <f.fainelli@gmail.com>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-rpi-kernel@lists.infradead.org>,
Jim Quinlan <james.quinlan@broadcom.com>,
Bjorn Helgaas <bhelgaas@google.com>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>
Subject: [PATCH v8 05/12] PCI: brcmstb: Add suspend and resume pm_ops
Date: Wed, 15 Jul 2020 10:35:08 -0400 [thread overview]
Message-ID: <20200715143530.9702-6-james.quinlan@broadcom.com> (raw)
In-Reply-To: <20200715143530.9702-1-james.quinlan@broadcom.com>
From: Jim Quinlan <jquinlan@broadcom.com>
Broadcom Set-top (BrcmSTB) boards typically support S2, S3, and S5 suspend
and resume. Now the PCIe driver may do so as well.
Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
drivers/pci/controller/pcie-brcmstb.c | 47 +++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index b7a222fde3c4..7c148eb65170 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -979,6 +979,47 @@ static void brcm_pcie_turn_off(struct brcm_pcie *pcie)
brcm_pcie_bridge_sw_init_set(pcie, 1);
}
+static int brcm_pcie_suspend(struct device *dev)
+{
+ struct brcm_pcie *pcie = dev_get_drvdata(dev);
+
+ brcm_pcie_turn_off(pcie);
+ clk_disable_unprepare(pcie->clk);
+
+ return 0;
+}
+
+static int brcm_pcie_resume(struct device *dev)
+{
+ struct brcm_pcie *pcie = dev_get_drvdata(dev);
+ void __iomem *base;
+ u32 tmp;
+ int ret;
+
+ base = pcie->base;
+ clk_prepare_enable(pcie->clk);
+
+ /* Take bridge out of reset so we can access the SERDES reg */
+ brcm_pcie_bridge_sw_init_set(pcie, 0);
+
+ /* SERDES_IDDQ = 0 */
+ tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
+ u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
+ writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
+
+ /* wait for serdes to be stable */
+ udelay(100);
+
+ ret = brcm_pcie_setup(pcie);
+ if (ret)
+ return ret;
+
+ if (pcie->msi)
+ brcm_msi_set_regs(pcie->msi);
+
+ return 0;
+}
+
static void __brcm_pcie_remove(struct brcm_pcie *pcie)
{
brcm_msi_remove(pcie);
@@ -1110,12 +1151,18 @@ static int brcm_pcie_probe(struct platform_device *pdev)
MODULE_DEVICE_TABLE(of, brcm_pcie_match);
+static const struct dev_pm_ops brcm_pcie_pm_ops = {
+ .suspend_noirq = brcm_pcie_suspend,
+ .resume_noirq = brcm_pcie_resume,
+};
+
static struct platform_driver brcm_pcie_driver = {
.probe = brcm_pcie_probe,
.remove = brcm_pcie_remove,
.driver = {
.name = "brcm-pcie",
.of_match_table = brcm_pcie_match,
+ .pm = &brcm_pcie_pm_ops,
},
};
module_platform_driver(brcm_pcie_driver);
--
2.17.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-07-15 14:36 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-15 14:35 [PATCH v8 00/12] PCI: brcmstb: enable PCIe for STB chips Jim Quinlan
2020-07-15 14:35 ` Jim Quinlan
2020-07-15 14:35 ` Jim Quinlan
2020-07-15 14:35 ` Jim Quinlan
2020-07-15 14:35 ` Jim Quinlan via iommu
2020-07-15 14:35 ` [PATCH v8 01/12] PCI: brcmstb: PCIE_BRCMSTB depends on ARCH_BRCMSTB Jim Quinlan
2020-07-15 14:35 ` [PATCH v8 02/12] ata: ahci_brcm: Fix use of BCM7216 reset controller Jim Quinlan
2020-07-15 14:35 ` [PATCH v8 03/12] dt-bindings: PCI: Add bindings for more Brcmstb chips Jim Quinlan
2020-07-15 14:35 ` Jim Quinlan
2020-07-15 14:35 ` [PATCH v8 04/12] PCI: brcmstb: Add bcm7278 register info Jim Quinlan
2020-07-15 14:35 ` Jim Quinlan
2020-07-15 14:35 ` Jim Quinlan [this message]
2020-07-15 14:35 ` [PATCH v8 05/12] PCI: brcmstb: Add suspend and resume pm_ops Jim Quinlan
2020-07-15 14:35 ` [PATCH v8 06/12] PCI: brcmstb: Add bcm7278 PERST# support Jim Quinlan
2020-07-15 14:35 ` Jim Quinlan
2020-07-15 14:35 ` [PATCH v8 07/12] PCI: brcmstb: Add control of rescal reset Jim Quinlan
2020-07-15 14:35 ` Jim Quinlan
2020-07-15 14:35 ` [PATCH v8 08/12] device core: Introduce DMA range map, supplanting dma_pfn_offset Jim Quinlan via iommu
2020-07-15 14:35 ` Jim Quinlan
2020-07-21 12:51 ` Christoph Hellwig
2020-07-22 22:37 ` Jim Quinlan via iommu
2020-07-22 22:37 ` Jim Quinlan
2020-07-15 14:35 ` [PATCH v8 09/12] PCI: brcmstb: Set additional internal memory DMA viewport sizes Jim Quinlan
2020-07-15 14:35 ` Jim Quinlan
2020-07-15 14:35 ` [PATCH v8 10/12] PCI: brcmstb: Accommodate MSI for older chips Jim Quinlan
2020-07-15 14:35 ` Jim Quinlan
2020-07-15 14:35 ` [PATCH v8 11/12] PCI: brcmstb: Set bus max burst size by chip type Jim Quinlan
2020-07-15 14:35 ` Jim Quinlan
2020-07-15 14:35 ` [PATCH v8 12/12] PCI: brcmstb: Add bcm7211, bcm7216, bcm7445, bcm7278 to match list Jim Quinlan
2020-07-15 14:35 ` Jim Quinlan
2020-07-20 23:27 ` [PATCH v8 00/12] PCI: brcmstb: enable PCIe for STB chips Florian Fainelli
2020-07-20 23:27 ` Florian Fainelli
2020-07-20 23:27 ` Florian Fainelli
2020-07-20 23:27 ` Florian Fainelli
2020-07-20 23:27 ` Florian Fainelli
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