From: Nicolin Chen <nicoleotsuka@gmail.com>
To: Arnaud Ferraris <arnaud.ferraris@collabora.com>
Cc: alsa-devel@alsa-project.org, Timur Tabi <timur@kernel.org>,
Xiubo Li <Xiubo.Lee@gmail.com>,
Liam Girdwood <lgirdwood@gmail.com>,
Takashi Iwai <tiwai@suse.com>, Rob Herring <robh+dt@kernel.org>,
linux-kernel@vger.kernel.org, Mark Brown <broonie@kernel.org>,
kernel@collabora.com, Fabio Estevam <festevam@gmail.com>
Subject: Re: [PATCH 0/4] ASoC: fsl_asrc: allow selecting arbitrary clocks
Date: Wed, 15 Jul 2020 13:46:38 -0700 [thread overview]
Message-ID: <20200715204636.GA14539@Asurada-Nvidia> (raw)
In-Reply-To: <0a56326b-27a9-d9f4-3923-8773963d7548@collabora.com>
On Wed, Jul 15, 2020 at 06:18:38PM +0200, Arnaud Ferraris wrote:
> Hi,
>
> Le 15/07/2020 à 16:05, Mark Brown a écrit :
> > On Tue, Jul 14, 2020 at 01:50:50PM -0700, Nicolin Chen wrote:
> > Anything wrong with ASRC selecting SSI1 clock for both cases? The
> > driver calculates the divisors based on the given clock rate, so
> > the final internal rate should be the same. If there's a problem,
> > I feel that's a separate bug.
>
> Calculations are indeed good, but then the clock selection setting in
> the ASRCSR register would also use SSI1 as the input clock, which
> doesn't work in our case.
Could you please elaborate why it doesn't work?
WARNING: multiple messages have this Message-ID (diff)
From: Nicolin Chen <nicoleotsuka@gmail.com>
To: Arnaud Ferraris <arnaud.ferraris@collabora.com>
Cc: Mark Brown <broonie@kernel.org>,
alsa-devel@alsa-project.org, Timur Tabi <timur@kernel.org>,
Xiubo Li <Xiubo.Lee@gmail.com>,
linux-kernel@vger.kernel.org, Takashi Iwai <tiwai@suse.com>,
Liam Girdwood <lgirdwood@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
kernel@collabora.com, Fabio Estevam <festevam@gmail.com>
Subject: Re: [PATCH 0/4] ASoC: fsl_asrc: allow selecting arbitrary clocks
Date: Wed, 15 Jul 2020 13:46:38 -0700 [thread overview]
Message-ID: <20200715204636.GA14539@Asurada-Nvidia> (raw)
In-Reply-To: <0a56326b-27a9-d9f4-3923-8773963d7548@collabora.com>
On Wed, Jul 15, 2020 at 06:18:38PM +0200, Arnaud Ferraris wrote:
> Hi,
>
> Le 15/07/2020 à 16:05, Mark Brown a écrit :
> > On Tue, Jul 14, 2020 at 01:50:50PM -0700, Nicolin Chen wrote:
> > Anything wrong with ASRC selecting SSI1 clock for both cases? The
> > driver calculates the divisors based on the given clock rate, so
> > the final internal rate should be the same. If there's a problem,
> > I feel that's a separate bug.
>
> Calculations are indeed good, but then the clock selection setting in
> the ASRCSR register would also use SSI1 as the input clock, which
> doesn't work in our case.
Could you please elaborate why it doesn't work?
next prev parent reply other threads:[~2020-07-15 20:48 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-02 14:22 [PATCH 0/4] ASoC: fsl_asrc: allow selecting arbitrary clocks Arnaud Ferraris
2020-07-02 14:22 ` Arnaud Ferraris
2020-07-02 14:22 ` Arnaud Ferraris
2020-07-02 14:22 ` [PATCH 1/4] dt-bindings: sound: fsl, asrc: add properties to select in/out clocks Arnaud Ferraris
2020-07-02 14:22 ` [PATCH 1/4] dt-bindings: sound: fsl,asrc: " Arnaud Ferraris
2020-07-02 14:22 ` [PATCH 1/4] dt-bindings: sound: fsl, asrc: " Arnaud Ferraris
2020-07-02 14:22 ` [PATCH 2/4] ASoC: fsl_asrc: allow using arbitrary input and output clocks Arnaud Ferraris
2020-07-02 14:22 ` Arnaud Ferraris
2020-07-02 14:22 ` Arnaud Ferraris
2020-07-02 17:42 ` kernel test robot
2020-07-02 21:33 ` kernel test robot
2020-07-02 14:22 ` [PATCH 3/4] ASoC: fsl_asrc: always use ratio for conversion Arnaud Ferraris
2020-07-02 14:22 ` Arnaud Ferraris
2020-07-02 14:22 ` Arnaud Ferraris
2020-07-02 14:22 ` [PATCH 4/4] ASoC: fsl_asrc: swap input and output clocks in capture mode Arnaud Ferraris
2020-07-02 14:22 ` Arnaud Ferraris
2020-07-02 14:22 ` Arnaud Ferraris
2020-07-02 19:34 ` kernel test robot
2020-07-02 18:42 ` [PATCH 0/4] ASoC: fsl_asrc: allow selecting arbitrary clocks Nicolin Chen
2020-07-02 18:42 ` Nicolin Chen
2020-07-02 18:42 ` Nicolin Chen
2020-07-03 9:38 ` Arnaud Ferraris
2020-07-03 9:38 ` Arnaud Ferraris
2020-07-14 16:20 ` Arnaud Ferraris
2020-07-14 16:20 ` Arnaud Ferraris
2020-07-14 20:15 ` Nicolin Chen
2020-07-14 20:15 ` Nicolin Chen
2020-07-14 20:27 ` Mark Brown
2020-07-14 20:27 ` Mark Brown
2020-07-14 20:50 ` Nicolin Chen
2020-07-14 20:50 ` Nicolin Chen
2020-07-15 14:05 ` Mark Brown
2020-07-15 14:05 ` Mark Brown
2020-07-15 16:18 ` Arnaud Ferraris
2020-07-15 16:18 ` Arnaud Ferraris
2020-07-15 16:22 ` Mark Brown
2020-07-15 16:22 ` Mark Brown
2020-07-15 16:32 ` Arnaud Ferraris
2020-07-15 16:32 ` Arnaud Ferraris
2020-07-15 20:46 ` Nicolin Chen [this message]
2020-07-15 20:46 ` Nicolin Chen
2020-07-16 9:54 ` Arnaud Ferraris
2020-07-16 9:54 ` Arnaud Ferraris
2020-07-15 21:03 ` Nicolin Chen
2020-07-15 21:03 ` Nicolin Chen
2020-07-16 12:18 ` Mark Brown
2020-07-16 12:18 ` Mark Brown
2020-07-16 14:26 ` Arnaud Ferraris
2020-07-16 14:26 ` Arnaud Ferraris
2020-07-17 11:16 ` Arnaud Ferraris
2020-07-17 11:16 ` Arnaud Ferraris
2020-07-17 11:16 ` Arnaud Ferraris
2020-07-23 5:46 ` Nicolin Chen
2020-07-23 5:46 ` Nicolin Chen
2020-07-23 5:46 ` Nicolin Chen
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