* [PATCH 01/10] drm/amd/display: update dml var
2020-07-10 20:33 [PATCH 00/10] DC Patches July 10, 2020 Rodrigo Siqueira
@ 2020-07-10 20:33 ` Rodrigo Siqueira
2020-07-10 20:33 ` [PATCH 02/10] drm/amd/display: Power down hardware if set mode is not called before timeout Rodrigo Siqueira
` (8 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Rodrigo Siqueira @ 2020-07-10 20:33 UTC (permalink / raw)
To: amd-gfx
Cc: Dmytro Laktyushkin, Eryk.Brol, Sunpeng.Li, Harry.Wentland,
qingqing.zhuo, Rodrigo.Siqueira, Aurabindo.Pillai,
Bhawanpreet.Lakha
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Update *DynamicMetadata variables for providing more flexibility.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
.../drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 8 +++-----
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 2 +-
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index 75dc4fe41731..b54814f11b74 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -2567,7 +2567,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
&v->VRatioPrefetchC[k],
&v->RequiredPrefetchPixDataBWLuma[k],
&v->RequiredPrefetchPixDataBWChroma[k],
- &v->NotEnoughTimeForDynamicMetadata,
+ &v->NotEnoughTimeForDynamicMetadata[k],
&v->Tno_bw[k],
&v->prefetch_vmrow_bw[k],
&v->Tdmdl_vm[k],
@@ -2686,7 +2686,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
v->FractionOfUrgentBandwidth = MaxTotalRDBandwidthNoUrgentBurst / v->ReturnBW;
- if (MaxTotalRDBandwidth <= v->ReturnBW && v->NotEnoughUrgentLatencyHiding == 0 && v->NotEnoughUrgentLatencyHidingPre == 0 && v->NotEnoughTimeForDynamicMetadata == 0 && !VRatioPrefetchMoreThan4
+ if (MaxTotalRDBandwidth <= v->ReturnBW && v->NotEnoughUrgentLatencyHiding == 0 && v->NotEnoughUrgentLatencyHidingPre == 0 && !VRatioPrefetchMoreThan4
&& !DestinationLineTimesForPrefetchLessThan2)
v->PrefetchModeSupported = true;
else {
@@ -2695,8 +2695,6 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
dml_print("DML: MaxTotalRDBandwidth:%f AvailReturnBandwidth:%f\n", MaxTotalRDBandwidth, v->ReturnBW);
dml_print("DML: VRatioPrefetch %s more than 4\n", (VRatioPrefetchMoreThan4) ? "is" : "is not");
dml_print("DML: DestinationLines for Prefetch %s less than 2\n", (DestinationLineTimesForPrefetchLessThan2) ? "is" : "is not");
- dml_print("DML: Not enough lines for dynamic meta is %s\n", (v->NotEnoughTimeForDynamicMetadata) ? "true" : "false");
-
}
if (v->PrefetchModeSupported == true && v->ImmediateFlipSupport == true) {
@@ -2786,7 +2784,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
}
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
- if (v->ErrorResult[k]) {
+ if (v->ErrorResult[k] || v->NotEnoughTimeForDynamicMetadata[k]) {
v->PrefetchModeSupported = false;
dml_print("DML: CalculatePrefetchSchedule ***failed***. Prefetch schedule violation. Results are NOT valid\n");
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index f615815c73bd..756d8eb1221c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -802,7 +802,7 @@ struct vba_vars_st {
unsigned int DCCCMaxCompressedBlock[DC__NUM_DPP__MAX];
unsigned int DCCCIndependent64ByteBlock[DC__NUM_DPP__MAX];
double VStartupMargin;
- bool NotEnoughTimeForDynamicMetadata;
+ bool NotEnoughTimeForDynamicMetadata[DC__NUM_DPP__MAX];
/* Missing from VBA */
unsigned int MaximumMaxVStartupLines;
--
2.27.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 02/10] drm/amd/display: Power down hardware if set mode is not called before timeout
2020-07-10 20:33 [PATCH 00/10] DC Patches July 10, 2020 Rodrigo Siqueira
2020-07-10 20:33 ` [PATCH 01/10] drm/amd/display: update dml var Rodrigo Siqueira
@ 2020-07-10 20:33 ` Rodrigo Siqueira
2020-07-10 20:33 ` [PATCH 03/10] drm/amd/display: reduce sr_xxx_time by 3 us when ppt disable Rodrigo Siqueira
` (7 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Rodrigo Siqueira @ 2020-07-10 20:33 UTC (permalink / raw)
To: amd-gfx
Cc: Sung Lee, Eryk.Brol, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, Aurabindo.Pillai, Bhawanpreet.Lakha,
Anthony Koo
From: Sung Lee <sung.lee@amd.com>
[WHY]
In headless systems, if set mode is not called, hardware will not be
powered down on boot, causing HW/SW discrepancies. Powering down
hardware on boot will ensure SW state is accurate.
[HOW]
Set a timer callback on boot for 10 seconds. If set mode is not called
within that time, power down hardware. Otherwise, do not power down.
Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 ++
drivers/gpu/drm/amd/display/dc/dc.h | 3 +
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 69 ++++++++++---------
.../amd/display/dc/dcn10/dcn10_hw_sequencer.h | 1 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_init.c | 1 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 1 +
.../gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 1 +
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 1 +
8 files changed, 51 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 942ceb0f6383..8d935020068f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2683,6 +2683,12 @@ void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
dal_irq_service_ack(dc->res_pool->irqs, src);
}
+void dc_power_down_on_boot(struct dc *dc)
+{
+ if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW &&
+ dc->hwss.power_down_on_boot)
+ dc->hwss.power_down_on_boot(dc);
+}
void dc_set_power_state(
struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 389edcf3f6ce..c2336ca3a9e0 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1029,6 +1029,7 @@ bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
*/
bool dc_commit_state(struct dc *dc, struct dc_state *context);
+void dc_power_down_on_boot(struct dc *dc);
struct dc_state *dc_create_state(struct dc *dc);
struct dc_state *dc_copy_state(struct dc_state *src_ctx);
@@ -1229,6 +1230,8 @@ void dc_set_power_state(
enum dc_acpi_cm_power_state power_state);
void dc_resume(struct dc *dc);
+void dc_power_down_on_boot(struct dc *dc);
+
#if defined(CONFIG_DRM_AMD_DC_HDCP)
/*
* HDCP Interfaces
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 6711ff908bcf..20466cad6ade 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1393,38 +1393,6 @@ void dcn10_init_hw(struct dc *dc)
}
}
- /* In headless boot cases, DIG may be turned
- * on which causes HW/SW discrepancies.
- * To avoid this, power down hardware on boot
- * if DIG is turned on and seamless boot not enabled
- */
- if (dc->config.power_down_display_on_boot) {
- struct dc_link *edp_link = get_edp_link(dc);
-
- if (edp_link &&
- edp_link->link_enc->funcs->is_dig_enabled &&
- edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
- dc->hwseq->funcs.edp_backlight_control &&
- dc->hwss.power_down &&
- dc->hwss.edp_power_control) {
- dc->hwseq->funcs.edp_backlight_control(edp_link, false);
- dc->hwss.power_down(dc);
- dc->hwss.edp_power_control(edp_link, false);
- } else {
- for (i = 0; i < dc->link_count; i++) {
- struct dc_link *link = dc->links[i];
-
- if (link->link_enc->funcs->is_dig_enabled &&
- link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
- dc->hwss.power_down) {
- dc->hwss.power_down(dc);
- break;
- }
-
- }
- }
- }
-
if (!is_optimized_init_done) {
for (i = 0; i < res_pool->audio_count; i++) {
@@ -1475,6 +1443,43 @@ void dcn10_init_hw(struct dc *dc)
}
+/* In headless boot cases, DIG may be turned
+ * on which causes HW/SW discrepancies.
+ * To avoid this, power down hardware on boot
+ * if DIG is turned on and seamless boot not enabled
+ */
+void dcn10_power_down_on_boot(struct dc *dc)
+{
+ int i = 0;
+
+ if (dc->config.power_down_display_on_boot) {
+ struct dc_link *edp_link = get_edp_link(dc);
+
+ if (edp_link &&
+ edp_link->link_enc->funcs->is_dig_enabled &&
+ edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
+ dc->hwseq->funcs.edp_backlight_control &&
+ dc->hwss.power_down &&
+ dc->hwss.edp_power_control) {
+ dc->hwseq->funcs.edp_backlight_control(edp_link, false);
+ dc->hwss.power_down(dc);
+ dc->hwss.edp_power_control(edp_link, false);
+ } else {
+ for (i = 0; i < dc->link_count; i++) {
+ struct dc_link *link = dc->links[i];
+
+ if (link->link_enc->funcs->is_dig_enabled &&
+ link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
+ dc->hwss.power_down) {
+ dc->hwss.power_down(dc);
+ break;
+ }
+
+ }
+ }
+ }
+}
+
void dcn10_reset_hw_ctx_wrap(
struct dc *dc,
struct dc_state *context)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index 42b6e016d71e..6d891166da8a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -109,6 +109,7 @@ void dcn10_program_pipe(
void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx);
void dcn10_init_hw(struct dc *dc);
void dcn10_init_pipes(struct dc *dc, struct dc_state *context);
+void dcn10_power_down_on_boot(struct dc *dc);
enum dc_status dce110_apply_ctx_to_hw(
struct dc *dc,
struct dc_state *context);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
index f6a790c49321..5c98b71c1d47 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
@@ -30,6 +30,7 @@
static const struct hw_sequencer_funcs dcn10_funcs = {
.program_gamut_remap = dcn10_program_gamut_remap,
.init_hw = dcn10_init_hw,
+ .power_down_on_boot = dcn10_power_down_on_boot,
.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
.apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
.post_unlock_program_front_end = dcn10_post_unlock_program_front_end,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
index bb9e9bec2f28..2380392b916e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
@@ -30,6 +30,7 @@
static const struct hw_sequencer_funcs dcn20_funcs = {
.program_gamut_remap = dcn10_program_gamut_remap,
.init_hw = dcn10_init_hw,
+ .power_down_on_boot = dcn10_power_down_on_boot,
.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
.apply_ctx_for_surface = NULL,
.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
index 8575de1a8ad2..177d0dc8927a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
@@ -31,6 +31,7 @@
static const struct hw_sequencer_funcs dcn21_funcs = {
.program_gamut_remap = dcn10_program_gamut_remap,
.init_hw = dcn10_init_hw,
+ .power_down_on_boot = dcn10_power_down_on_boot,
.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
.apply_ctx_for_surface = NULL,
.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 066a2a723c12..720ce5e458d8 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -56,6 +56,7 @@ struct hw_sequencer_funcs {
/* Pipe Programming Related */
void (*init_hw)(struct dc *dc);
+ void (*power_down_on_boot)(struct dc *dc);
void (*enable_accelerated_mode)(struct dc *dc,
struct dc_state *context);
enum dc_status (*apply_ctx_to_hw)(struct dc *dc,
--
2.27.0
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 03/10] drm/amd/display: reduce sr_xxx_time by 3 us when ppt disable
2020-07-10 20:33 [PATCH 00/10] DC Patches July 10, 2020 Rodrigo Siqueira
2020-07-10 20:33 ` [PATCH 01/10] drm/amd/display: update dml var Rodrigo Siqueira
2020-07-10 20:33 ` [PATCH 02/10] drm/amd/display: Power down hardware if set mode is not called before timeout Rodrigo Siqueira
@ 2020-07-10 20:33 ` Rodrigo Siqueira
2020-07-10 20:33 ` Rodrigo Siqueira
` (6 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Rodrigo Siqueira @ 2020-07-10 20:33 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, Chiawen Huang, Aurabindo.Pillai, Tony Cheng,
Bhawanpreet.Lakha
From: Chiawen Huang <chiawen.huang@amd.com>
[Why]
when ppt disabled, the watermark doesn't get fine tune causing
underflow.
[How]
It is a temporary solution to reduce sr_xxx_time by 3 us when ppt
disable.
Signed-off-by: Chiawen Huang <chiawen.huang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
.../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 43 ++++++++++++++++++-
.../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 13 +++++-
.../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h | 1 +
.../amd/display/dc/inc/hw/clk_mgr_internal.h | 1 +
4 files changed, 55 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 9b4807f52381..c664404a75d4 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -634,6 +634,42 @@ static struct wm_table lpddr4_wm_table = {
}
};
+static struct wm_table lpddr4_wm_table_with_disabled_ppt = {
+ .entries = {
+ {
+ .wm_inst = WM_A,
+ .wm_type = WM_TYPE_PSTATE_CHG,
+ .pstate_latency_us = 11.65333,
+ .sr_exit_time_us = 8.32,
+ .sr_enter_plus_exit_time_us = 9.38,
+ .valid = true,
+ },
+ {
+ .wm_inst = WM_B,
+ .wm_type = WM_TYPE_PSTATE_CHG,
+ .pstate_latency_us = 11.65333,
+ .sr_exit_time_us = 9.82,
+ .sr_enter_plus_exit_time_us = 11.196,
+ .valid = true,
+ },
+ {
+ .wm_inst = WM_C,
+ .wm_type = WM_TYPE_PSTATE_CHG,
+ .pstate_latency_us = 11.65333,
+ .sr_exit_time_us = 9.89,
+ .sr_enter_plus_exit_time_us = 11.24,
+ .valid = true,
+ },
+ {
+ .wm_inst = WM_D,
+ .wm_type = WM_TYPE_PSTATE_CHG,
+ .pstate_latency_us = 11.65333,
+ .sr_exit_time_us = 9.748,
+ .sr_enter_plus_exit_time_us = 11.102,
+ .valid = true,
+ },
+ }
+};
static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
{
@@ -738,6 +774,7 @@ void rn_clk_mgr_construct(
struct clk_log_info log_info = {0};
clk_mgr->smu_ver = rn_vbios_smu_get_smu_version(clk_mgr);
+ clk_mgr->periodic_retraining_disabled = rn_vbios_smu_is_periodic_retraining_disabled(clk_mgr);
/* SMU Version 55.51.0 and up no longer have an issue
* that needs to limit minimum dispclk */
@@ -752,7 +789,11 @@ void rn_clk_mgr_construct(
clk_mgr->base.dentist_vco_freq_khz = 3600000;
if (ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) {
- rn_bw_params.wm_table = lpddr4_wm_table;
+ if (clk_mgr->periodic_retraining_disabled) {
+ rn_bw_params.wm_table = lpddr4_wm_table_with_disabled_ppt;
+ } else {
+ rn_bw_params.wm_table = lpddr4_wm_table;
+ }
} else {
rn_bw_params.wm_table = ddr4_wm_table;
}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
index d2facbb114d3..9a374522e963 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
@@ -52,7 +52,8 @@
#define VBIOSSMC_MSG_GetFclkFrequency 0xB
#define VBIOSSMC_MSG_SetDisplayCount 0xC
#define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0xD
-#define VBIOSSMC_MSG_UpdatePmeRestore 0xE
+#define VBIOSSMC_MSG_UpdatePmeRestore 0xE
+#define VBIOSSMC_MSG_IsPeriodicRetrainingDisabled 0xF
#define VBIOSSMC_Status_BUSY 0x0
#define VBIOSSMC_Result_OK 0x1
@@ -100,7 +101,7 @@ int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned
result = rn_smu_wait_for_response(clk_mgr, 10, 1000);
- ASSERT(result == VBIOSSMC_Result_OK);
+ ASSERT(result == VBIOSSMC_Result_OK || result == VBIOSSMC_Result_UnknownCmd);
/* Actual dispclk set is returned in the parameter register */
return REG_READ(MP1_SMN_C2PMSG_83);
@@ -232,3 +233,11 @@ void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)
VBIOSSMC_MSG_UpdatePmeRestore,
0);
}
+
+int rn_vbios_smu_is_periodic_retraining_disabled(struct clk_mgr_internal *clk_mgr)
+{
+ return rn_vbios_smu_send_msg_with_param(
+ clk_mgr,
+ VBIOSSMC_MSG_IsPeriodicRetrainingDisabled,
+ 0);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h
index ccc01879c9d4..3e5df27aa96f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h
@@ -36,5 +36,6 @@ int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_
void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, int display_count);
void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
+int rn_vbios_smu_is_periodic_retraining_disabled(struct clk_mgr_internal *clk_mgr);
#endif /* DAL_DC_DCN10_RV1_CLK_MGR_VBIOS_SMU_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index b3b8b46d293e..4e6e18bbef5d 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -270,6 +270,7 @@ struct clk_mgr_internal {
enum dm_pp_clocks_state max_clks_state;
enum dm_pp_clocks_state cur_min_clks_state;
+ bool periodic_retraining_disabled;
unsigned int cur_phyclk_req_table[MAX_PIPES * 2];
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
--
2.27.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 04/10] drm/amd/display: OLED panel backlight adjust not work with external display connected
2020-07-10 20:33 [PATCH 00/10] DC Patches July 10, 2020 Rodrigo Siqueira
@ 2020-07-10 20:33 ` Rodrigo Siqueira
2020-07-10 20:33 ` [PATCH 02/10] drm/amd/display: Power down hardware if set mode is not called before timeout Rodrigo Siqueira
` (8 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Rodrigo Siqueira @ 2020-07-10 20:33 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, stable, Aurabindo.Pillai, hersen wu,
Bhawanpreet.Lakha, Nicholas Kazlauskas
From: hersen wu <hersenxs.wu@amd.com>
[Why]
amdgpu_dm->backlight_caps is for single eDP only. the caps are upddated
for very connector. Real eDP caps will be overwritten by other external
display. For OLED panel, caps->aux_support is set to 1 for OLED pnael.
after external connected, caps+.aux_support is set to 0. This causes
OLED backlight adjustment not work.
[How]
within update_conector_ext_caps, backlight caps will be updated only for
eDP connector.
Cc: stable@vger.kernel.org
Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index b4e120e95438..5569e0500734 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2019,6 +2019,7 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
struct amdgpu_display_manager *dm;
struct drm_connector *conn_base;
struct amdgpu_device *adev;
+ struct dc_link *link = NULL;
static const u8 pre_computed_values[] = {
50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98};
@@ -2026,6 +2027,10 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
if (!aconnector || !aconnector->dc_link)
return;
+ link = aconnector->dc_link;
+ if (link->connector_signal != SIGNAL_TYPE_EDP)
+ return;
+
conn_base = &aconnector->base;
adev = conn_base->dev->dev_private;
dm = &adev->dm;
--
2.27.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 04/10] drm/amd/display: OLED panel backlight adjust not work with external display connected
@ 2020-07-10 20:33 ` Rodrigo Siqueira
0 siblings, 0 replies; 18+ messages in thread
From: Rodrigo Siqueira @ 2020-07-10 20:33 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, Eryk.Brol, hersen wu, stable,
Nicholas Kazlauskas
From: hersen wu <hersenxs.wu@amd.com>
[Why]
amdgpu_dm->backlight_caps is for single eDP only. the caps are upddated
for very connector. Real eDP caps will be overwritten by other external
display. For OLED panel, caps->aux_support is set to 1 for OLED pnael.
after external connected, caps+.aux_support is set to 0. This causes
OLED backlight adjustment not work.
[How]
within update_conector_ext_caps, backlight caps will be updated only for
eDP connector.
Cc: stable@vger.kernel.org
Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index b4e120e95438..5569e0500734 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2019,6 +2019,7 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
struct amdgpu_display_manager *dm;
struct drm_connector *conn_base;
struct amdgpu_device *adev;
+ struct dc_link *link = NULL;
static const u8 pre_computed_values[] = {
50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98};
@@ -2026,6 +2027,10 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
if (!aconnector || !aconnector->dc_link)
return;
+ link = aconnector->dc_link;
+ if (link->connector_signal != SIGNAL_TYPE_EDP)
+ return;
+
conn_base = &aconnector->base;
adev = conn_base->dev->dev_private;
dm = &adev->dm;
--
2.27.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 04/10] drm/amd/display: OLED panel backlight adjust not work with external display connected
2020-07-10 20:33 ` Rodrigo Siqueira
@ 2020-07-16 0:27 ` Sasha Levin
-1 siblings, 0 replies; 18+ messages in thread
From: Sasha Levin @ 2020-07-16 0:27 UTC (permalink / raw)
To: Sasha Levin, Rodrigo Siqueira, hersen wu, amd-gfx
Cc: Sunpeng.Li, Harry.Wentland, stable
Hi
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.7.8, v5.4.51, v4.19.132, v4.14.188, v4.9.230, v4.4.230.
v5.7.8: Build OK!
v5.4.51: Failed to apply! Possible dependencies:
945628101be55 ("drm/amd/display: Add backlight support via AUX")
v4.19.132: Failed to apply! Possible dependencies:
0cafc82fae415 ("drm/amd/display: set backlight level limit to 1")
11c3ee48bd7c2 ("drm/amdgpu/display: add support for LVDS (v5)")
1e7e86c43f38d ("drm/amd/display: decouple front and backend pgm using dpms_off as backend enable flag")
206bbafe00dca ("drm/amd: Query and use ACPI backlight caps")
262485a50fd45 ("drm/amd/display: Expand dc to use 16.16 bit backlight")
694d0775ca94b ("drm/amd: Don't fail on backlight = 0")
8c3db1284a016 ("drm/amdgpu: fill in amdgpu_dm_remove_sink_from_freesync_module")
945628101be55 ("drm/amd/display: Add backlight support via AUX")
98e6436d3af5f ("drm/amd/display: Refactor FreeSync module")
aa9c4abe466ac ("drm/amd/display: Refactor FPGA-specific link setup")
v4.14.188: Failed to apply! Possible dependencies:
1b0c0f9dc5ca6 ("drm/amdgpu: move userptr BOs to CPU domain during CS v2")
1ed3d2567c800 ("drm/amdgpu: keep the MMU lock until the update ends v4")
3fe89771cb0a6 ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
4562236b3bc0a ("drm/amd/dc: Add dc display driver (v2)")
60de1c1740f39 ("drm/amdgpu: use a rw_semaphore for MMU notifiers")
945628101be55 ("drm/amd/display: Add backlight support via AUX")
9a18999640fa6 ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
9cca0b8e5df0a ("drm/amdgpu: move amdgpu_cs_sysvm_access_required into find_mapping")
a216ab09955d6 ("drm/amdgpu: fix userptr put_page handling")
b72cf4fca2bb7 ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
ca666a3c298f8 ("drm/amdgpu: stop using BO status for user pages")
v4.9.230: Failed to apply! Possible dependencies:
1cec20f0ea0e3 ("dma-buf: Restart reservation_object_wait_timeout_rcu() after writes")
3fe89771cb0a6 ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
4562236b3bc0a ("drm/amd/dc: Add dc display driver (v2)")
4df654d293c64 ("drm/amdgpu: move amdgpu_uvd structure to uvd header")
5e5681788befb ("drm/amdgpu: move amdgpu_vce structure to vce header")
660e855813f78 ("amdgpu: use drm sync objects for shared semaphores (v6)")
78010cd9736ec ("dma-buf/fence: add an lockdep_assert_held()")
945628101be55 ("drm/amd/display: Add backlight support via AUX")
95aa13f6b196d ("drm/amdgpu: move amdgpu_vcn structure to vcn header")
95d0906f85065 ("drm/amdgpu: add initial vcn support and decode tests")
9a18999640fa6 ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
b636922553ee2 ("drm/amdgpu: only move VM BOs in the LRU during validation v2")
b72cf4fca2bb7 ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
f54d1867005c3 ("dma-buf: Rename struct fence to dma_fence")
fedf54132d241 ("dma-buf: Restart reservation_object_get_fences_rcu() after writes")
v4.4.230: Failed to apply! Possible dependencies:
1f7371b2a5faf ("drm/amd/powerplay: add basic powerplay framework")
288912cb95d15 ("drm/amdgpu: use $(src) in Makefile (v2)")
37cd0ca204a55 ("drm/amdgpu: unify AMDGPU_CTX_MAX_CS_PENDING and amdgpu_sched_jobs")
3c0eea6c35d93 ("drm/amdgpu: put VM page tables directly into duplicates list")
3f99dd814a6fd ("drm/amdgpu: save and restore UVD context with suspend and resume")
4325198180e5a ("drm/amdgpu: remove GART page addr array")
4562236b3bc0a ("drm/amd/dc: Add dc display driver (v2)")
4acabfe3793eb ("drm/amdgpu: fix num_ibs check")
4df654d293c64 ("drm/amdgpu: move amdgpu_uvd structure to uvd header")
50838c8cc413d ("drm/amdgpu: add proper job alloc/free functions")
56467ebfb2548 ("drm/amdgpu: split VM PD and PT handling during CS")
5e5681788befb ("drm/amdgpu: move amdgpu_vce structure to vce header")
7270f8391df1a ("drm/amdgpu: add amdgpu_set_ib_value helper (v2)")
945628101be55 ("drm/amd/display: Add backlight support via AUX")
95aa13f6b196d ("drm/amdgpu: move amdgpu_vcn structure to vcn header")
9a18999640fa6 ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
a1d29476d666f ("drm/amdgpu: optionally enable GART debugfs file")
a8fe58cec351c ("drm/amd: add ACP driver support")
c036554170fcc ("drm/amdgpu: handle more than 10 UVD sessions (v2)")
c3cca41e6249e ("drm/amdgpu: cleanup amdgpu_cs_parser structure")
cadf97b196a1e ("drm/amdgpu: clean up non-scheduler code path (v2)")
cd75dc6887f1e ("drm/amdgpu: separate pushing CS to scheduler")
d71518b5aa7c9 ("drm/amdgpu: cleanup in kernel job submission")
d7af97dbccf01 ("drm/amdgpu: send UVD IB tests directly to the ring again")
d8e0cae645504 ("drm/amdgpu: validate duplicates first")
f69f90a113f28 ("drm/amdgpu: fix amdgpu_cs_get_threshold_for_moves handling")
fdba11f4079ec ("drm/amdgpu: move all Kconfig options to amdgpu/Kconfig")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks
Sasha
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 04/10] drm/amd/display: OLED panel backlight adjust not work with external display connected
@ 2020-07-16 0:27 ` Sasha Levin
0 siblings, 0 replies; 18+ messages in thread
From: Sasha Levin @ 2020-07-16 0:27 UTC (permalink / raw)
To: Sasha Levin, Rodrigo Siqueira, hersen wu, amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, stable, stable
Hi
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.7.8, v5.4.51, v4.19.132, v4.14.188, v4.9.230, v4.4.230.
v5.7.8: Build OK!
v5.4.51: Failed to apply! Possible dependencies:
945628101be55 ("drm/amd/display: Add backlight support via AUX")
v4.19.132: Failed to apply! Possible dependencies:
0cafc82fae415 ("drm/amd/display: set backlight level limit to 1")
11c3ee48bd7c2 ("drm/amdgpu/display: add support for LVDS (v5)")
1e7e86c43f38d ("drm/amd/display: decouple front and backend pgm using dpms_off as backend enable flag")
206bbafe00dca ("drm/amd: Query and use ACPI backlight caps")
262485a50fd45 ("drm/amd/display: Expand dc to use 16.16 bit backlight")
694d0775ca94b ("drm/amd: Don't fail on backlight = 0")
8c3db1284a016 ("drm/amdgpu: fill in amdgpu_dm_remove_sink_from_freesync_module")
945628101be55 ("drm/amd/display: Add backlight support via AUX")
98e6436d3af5f ("drm/amd/display: Refactor FreeSync module")
aa9c4abe466ac ("drm/amd/display: Refactor FPGA-specific link setup")
v4.14.188: Failed to apply! Possible dependencies:
1b0c0f9dc5ca6 ("drm/amdgpu: move userptr BOs to CPU domain during CS v2")
1ed3d2567c800 ("drm/amdgpu: keep the MMU lock until the update ends v4")
3fe89771cb0a6 ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
4562236b3bc0a ("drm/amd/dc: Add dc display driver (v2)")
60de1c1740f39 ("drm/amdgpu: use a rw_semaphore for MMU notifiers")
945628101be55 ("drm/amd/display: Add backlight support via AUX")
9a18999640fa6 ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
9cca0b8e5df0a ("drm/amdgpu: move amdgpu_cs_sysvm_access_required into find_mapping")
a216ab09955d6 ("drm/amdgpu: fix userptr put_page handling")
b72cf4fca2bb7 ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
ca666a3c298f8 ("drm/amdgpu: stop using BO status for user pages")
v4.9.230: Failed to apply! Possible dependencies:
1cec20f0ea0e3 ("dma-buf: Restart reservation_object_wait_timeout_rcu() after writes")
3fe89771cb0a6 ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
4562236b3bc0a ("drm/amd/dc: Add dc display driver (v2)")
4df654d293c64 ("drm/amdgpu: move amdgpu_uvd structure to uvd header")
5e5681788befb ("drm/amdgpu: move amdgpu_vce structure to vce header")
660e855813f78 ("amdgpu: use drm sync objects for shared semaphores (v6)")
78010cd9736ec ("dma-buf/fence: add an lockdep_assert_held()")
945628101be55 ("drm/amd/display: Add backlight support via AUX")
95aa13f6b196d ("drm/amdgpu: move amdgpu_vcn structure to vcn header")
95d0906f85065 ("drm/amdgpu: add initial vcn support and decode tests")
9a18999640fa6 ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
b636922553ee2 ("drm/amdgpu: only move VM BOs in the LRU during validation v2")
b72cf4fca2bb7 ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
f54d1867005c3 ("dma-buf: Rename struct fence to dma_fence")
fedf54132d241 ("dma-buf: Restart reservation_object_get_fences_rcu() after writes")
v4.4.230: Failed to apply! Possible dependencies:
1f7371b2a5faf ("drm/amd/powerplay: add basic powerplay framework")
288912cb95d15 ("drm/amdgpu: use $(src) in Makefile (v2)")
37cd0ca204a55 ("drm/amdgpu: unify AMDGPU_CTX_MAX_CS_PENDING and amdgpu_sched_jobs")
3c0eea6c35d93 ("drm/amdgpu: put VM page tables directly into duplicates list")
3f99dd814a6fd ("drm/amdgpu: save and restore UVD context with suspend and resume")
4325198180e5a ("drm/amdgpu: remove GART page addr array")
4562236b3bc0a ("drm/amd/dc: Add dc display driver (v2)")
4acabfe3793eb ("drm/amdgpu: fix num_ibs check")
4df654d293c64 ("drm/amdgpu: move amdgpu_uvd structure to uvd header")
50838c8cc413d ("drm/amdgpu: add proper job alloc/free functions")
56467ebfb2548 ("drm/amdgpu: split VM PD and PT handling during CS")
5e5681788befb ("drm/amdgpu: move amdgpu_vce structure to vce header")
7270f8391df1a ("drm/amdgpu: add amdgpu_set_ib_value helper (v2)")
945628101be55 ("drm/amd/display: Add backlight support via AUX")
95aa13f6b196d ("drm/amdgpu: move amdgpu_vcn structure to vcn header")
9a18999640fa6 ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
a1d29476d666f ("drm/amdgpu: optionally enable GART debugfs file")
a8fe58cec351c ("drm/amd: add ACP driver support")
c036554170fcc ("drm/amdgpu: handle more than 10 UVD sessions (v2)")
c3cca41e6249e ("drm/amdgpu: cleanup amdgpu_cs_parser structure")
cadf97b196a1e ("drm/amdgpu: clean up non-scheduler code path (v2)")
cd75dc6887f1e ("drm/amdgpu: separate pushing CS to scheduler")
d71518b5aa7c9 ("drm/amdgpu: cleanup in kernel job submission")
d7af97dbccf01 ("drm/amdgpu: send UVD IB tests directly to the ring again")
d8e0cae645504 ("drm/amdgpu: validate duplicates first")
f69f90a113f28 ("drm/amdgpu: fix amdgpu_cs_get_threshold_for_moves handling")
fdba11f4079ec ("drm/amdgpu: move all Kconfig options to amdgpu/Kconfig")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks
Sasha
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 05/10] drm/amd/display: p-state warning occurs while changing resolution from 120hz to 60hz
2020-07-10 20:33 [PATCH 00/10] DC Patches July 10, 2020 Rodrigo Siqueira
` (3 preceding siblings ...)
2020-07-10 20:33 ` Rodrigo Siqueira
@ 2020-07-10 20:33 ` Rodrigo Siqueira
2020-07-10 20:33 ` [PATCH 06/10] drm/amd/display: fix dcn3 p_state_change_support validation Rodrigo Siqueira
` (4 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Rodrigo Siqueira @ 2020-07-10 20:33 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, Aurabindo.Pillai, hersen wu, Bhawanpreet.Lakha,
Nicholas Kazlauskas
From: hersen wu <hersenxs.wu@amd.com>
[Why]
new calculated dispclk, dppclk are stored in
context->bw_ctx.bw.dcn.clk.dispclk_khz, dppclk_khz. Current dispclk,
dppclk are from dc->clk_mgr->clks.dispclk_khz. dcn_validate_bandwidth
compute new dispclk, dppclk. dispclk will put in use after
optimize_bandwidth when ramp_up_dispclk_with_dpp is called. There are
two places for dppclk be put in use. One location is the same as the
location as dispclk. Another is within update_dchubp_dpp which happens
between pre_bandwidth and optimize_bandwidth. dppclk updated within
update_dchubp_dpp will cause new clock values of dispclk and dppclk not
be in use at the same time. when clocks are decreased, this may cause
dppclk is lower than current configuration and let pipe stuck. for
example, eDP + external dp, change resolution of DP from 1920x1080x144hz
to 1280x960x60hz.
before change: dispclk = 337889 dppclk = 337889
change mode, dcn_validate_bandwidth calculate
dispclk = 143122 dppclk = 143122
update_dchubp_dpp be executed before dispclk be updated,
dispclk = 337889, but dppclk use new value dispclk /2 =
168944. this will cause pipe pstate warning issue.
[How]
between pre_bandwidth and optimize_bandwidth, while dispclk is going to
be decreased, keep dppclk = dispclk
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 36 +++++++++++++++++--
1 file changed, 34 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 20466cad6ade..e8ba55401148 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2462,14 +2462,46 @@ static void dcn10_update_dchubp_dpp(
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
struct plane_size size = plane_state->plane_size;
unsigned int compat_level = 0;
+ bool should_divided_by_2 = false;
/* depends on DML calculation, DPP clock value may change dynamically */
/* If request max dpp clk is lower than current dispclk, no need to
* divided by 2
*/
if (plane_state->update_flags.bits.full_update) {
- bool should_divided_by_2 = context->bw_ctx.bw.dcn.clk.dppclk_khz <=
- dc->clk_mgr->clks.dispclk_khz / 2;
+
+ /* new calculated dispclk, dppclk are stored in
+ * context->bw_ctx.bw.dcn.clk.dispclk_khz / dppclk_khz. current
+ * dispclk, dppclk are from dc->clk_mgr->clks.dispclk_khz.
+ * dcn_validate_bandwidth compute new dispclk, dppclk.
+ * dispclk will put in use after optimize_bandwidth when
+ * ramp_up_dispclk_with_dpp is called.
+ * there are two places for dppclk be put in use. One location
+ * is the same as the location as dispclk. Another is within
+ * update_dchubp_dpp which happens between pre_bandwidth and
+ * optimize_bandwidth.
+ * dppclk updated within update_dchubp_dpp will cause new
+ * clock values of dispclk and dppclk not be in use at the same
+ * time. when clocks are decreased, this may cause dppclk is
+ * lower than previous configuration and let pipe stuck.
+ * for example, eDP + external dp, change resolution of DP from
+ * 1920x1080x144hz to 1280x960x60hz.
+ * before change: dispclk = 337889 dppclk = 337889
+ * change mode, dcn_validate_bandwidth calculate
+ * dispclk = 143122 dppclk = 143122
+ * update_dchubp_dpp be executed before dispclk be updated,
+ * dispclk = 337889, but dppclk use new value dispclk /2 =
+ * 168944. this will cause pipe pstate warning issue.
+ * solution: between pre_bandwidth and optimize_bandwidth, while
+ * dispclk is going to be decreased, keep dppclk = dispclk
+ **/
+ if (context->bw_ctx.bw.dcn.clk.dispclk_khz <
+ dc->clk_mgr->clks.dispclk_khz)
+ should_divided_by_2 = false;
+ else
+ should_divided_by_2 =
+ context->bw_ctx.bw.dcn.clk.dppclk_khz <=
+ dc->clk_mgr->clks.dispclk_khz / 2;
dpp->funcs->dpp_dppclk_control(
dpp,
--
2.27.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 06/10] drm/amd/display: fix dcn3 p_state_change_support validation
2020-07-10 20:33 [PATCH 00/10] DC Patches July 10, 2020 Rodrigo Siqueira
` (4 preceding siblings ...)
2020-07-10 20:33 ` [PATCH 05/10] drm/amd/display: p-state warning occurs while changing resolution from 120hz to 60hz Rodrigo Siqueira
@ 2020-07-10 20:33 ` Rodrigo Siqueira
2020-07-13 1:30 ` Li, Dennis
2020-07-10 20:33 ` [PATCH 07/10] drm/amd/display: [FW Promotion] Release 0.0.24 Rodrigo Siqueira
` (3 subsequent siblings)
9 siblings, 1 reply; 18+ messages in thread
From: Rodrigo Siqueira @ 2020-07-10 20:33 UTC (permalink / raw)
To: amd-gfx
Cc: Dmytro Laktyushkin, Eryk.Brol, Sunpeng.Li, Harry.Wentland,
qingqing.zhuo, Rodrigo.Siqueira, Aurabindo.Pillai, Alvin Lee,
Bhawanpreet.Lakha
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Our validation is a known mess with actual validation mixed with
topology configuration. This change makes sure topolgical validation is
completed before any topology changes are made so we do not run into
issues where we merge and split a pipe over the course of a single call.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 46 ++++++++++++++++---
1 file changed, 39 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index d7ba895de765..653a571e366d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -1870,12 +1870,14 @@ static bool dcn30_split_stream_for_mpc_or_odm(
return true;
}
-static bool dcn30_fast_validate_bw(
+
+static bool dcn30_internal_validate_bw(
struct dc *dc,
struct dc_state *context,
display_e2e_pipe_params_st *pipes,
int *pipe_cnt_out,
- int *vlevel_out)
+ int *vlevel_out,
+ bool fast_validate)
{
bool out = false;
bool repopulate_pipes = false;
@@ -1898,7 +1900,38 @@ static bool dcn30_fast_validate_bw(
dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
- vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
+ if (!fast_validate) {
+ /*
+ * DML favors voltage over p-state, but we're more interested in
+ * supporting p-state over voltage. We can't support p-state in
+ * prefetch mode > 0 so try capping the prefetch mode to start.
+ */
+ context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
+ dm_allow_self_refresh_and_mclk_switch;
+ vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
+ /* This may adjust vlevel and maxMpcComb */
+ if (vlevel < context->bw_ctx.dml.soc.num_states)
+ vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
+ }
+ if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
+ vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
+ /*
+ * If mode is unsupported or there's still no p-state support then
+ * fall back to favoring voltage.
+ *
+ * We don't actually support prefetch mode 2, so require that we
+ * at least support prefetch mode 1.
+ */
+ context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
+ dm_allow_self_refresh;
+
+ vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
+ if (vlevel < context->bw_ctx.dml.soc.num_states) {
+ memset(split, 0, sizeof(split));
+ memset(merge, 0, sizeof(merge));
+ vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
+ }
+ }
dml_log_mode_support_params(&context->bw_ctx.dml);
@@ -1938,8 +1971,6 @@ static bool dcn30_fast_validate_bw(
pipe_idx++;
}
- vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
-
/* merge pipes if necessary */
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
@@ -2187,7 +2218,8 @@ static void dcn30_calculate_wm(
}
}
-bool dcn30_validate_bandwidth(struct dc *dc, struct dc_state *context,
+bool dcn30_validate_bandwidth(struct dc *dc,
+ struct dc_state *context,
bool fast_validate)
{
bool out = false;
@@ -2201,7 +2233,7 @@ bool dcn30_validate_bandwidth(struct dc *dc, struct dc_state *context,
BW_VAL_TRACE_COUNT();
- out = dcn30_fast_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel);
+ out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
if (pipe_cnt == 0)
goto validate_out;
--
2.27.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* RE: [PATCH 06/10] drm/amd/display: fix dcn3 p_state_change_support validation
2020-07-10 20:33 ` [PATCH 06/10] drm/amd/display: fix dcn3 p_state_change_support validation Rodrigo Siqueira
@ 2020-07-13 1:30 ` Li, Dennis
0 siblings, 0 replies; 18+ messages in thread
From: Li, Dennis @ 2020-07-13 1:30 UTC (permalink / raw)
To: Siqueira, Rodrigo, amd-gfx@lists.freedesktop.org
Cc: Brol, Eryk, Li, Sun peng (Leo), Lakha, Bhawanpreet,
Zhuo, Qingqing, Siqueira, Rodrigo, Laktyushkin, Dmytro,
Pillai, Aurabindo, Wentland, Harry, Lee, Alvin
[AMD Official Use Only - Internal Distribution Only]
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Rodrigo Siqueira
Sent: Saturday, July 11, 2020 4:33 AM
To: amd-gfx@lists.freedesktop.org
Cc: Laktyushkin, Dmytro <Dmytro.Laktyushkin@amd.com>; Brol, Eryk <Eryk.Brol@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Zhuo, Qingqing <Qingqing.Zhuo@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Lee, Alvin <Alvin.Lee2@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>
Subject: [PATCH 06/10] drm/amd/display: fix dcn3 p_state_change_support validation
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Our validation is a known mess with actual validation mixed with topology configuration. This change makes sure topolgical validation is completed before any topology changes are made so we do not run into issues where we merge and split a pipe over the course of a single call.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 46 ++++++++++++++++---
1 file changed, 39 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index d7ba895de765..653a571e366d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -1870,12 +1870,14 @@ static bool dcn30_split_stream_for_mpc_or_odm(
return true;
}
-static bool dcn30_fast_validate_bw(
+
+static bool dcn30_internal_validate_bw(
struct dc *dc,
struct dc_state *context,
display_e2e_pipe_params_st *pipes,
int *pipe_cnt_out,
- int *vlevel_out)
+ int *vlevel_out,
+ bool fast_validate)
{
bool out = false;
bool repopulate_pipes = false;
@@ -1898,7 +1900,38 @@ static bool dcn30_fast_validate_bw(
dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
- vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
+ if (!fast_validate) {
+ /*
+ * DML favors voltage over p-state, but we're more interested in
+ * supporting p-state over voltage. We can't support p-state in
+ * prefetch mode > 0 so try capping the prefetch mode to start.
+ */
+ context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
+ dm_allow_self_refresh_and_mclk_switch;
+ vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
+ /* This may adjust vlevel and maxMpcComb */
+ if (vlevel < context->bw_ctx.dml.soc.num_states)
+ vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
+ }
+ if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
+ vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
+ /*
+ * If mode is unsupported or there's still no p-state support then
+ * fall back to favoring voltage.
+ *
+ * We don't actually support prefetch mode 2, so require that we
+ * at least support prefetch mode 1.
+ */
+ context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
+ dm_allow_self_refresh;
+
+ vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
+ if (vlevel < context->bw_ctx.dml.soc.num_states) {
+ memset(split, 0, sizeof(split));
+ memset(merge, 0, sizeof(merge));
[Dennis] It seems that the above code is wrong. Should they be the following:
memset(split, 0, sizeof(*split));
memset(merge, 0, sizeof(*merge));
+ vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
+ }
+ }
dml_log_mode_support_params(&context->bw_ctx.dml);
@@ -1938,8 +1971,6 @@ static bool dcn30_fast_validate_bw(
pipe_idx++;
}
- vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
-
/* merge pipes if necessary */
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; @@ -2187,7 +2218,8 @@ static void dcn30_calculate_wm(
}
}
-bool dcn30_validate_bandwidth(struct dc *dc, struct dc_state *context,
+bool dcn30_validate_bandwidth(struct dc *dc,
+ struct dc_state *context,
bool fast_validate)
{
bool out = false;
@@ -2201,7 +2233,7 @@ bool dcn30_validate_bandwidth(struct dc *dc, struct dc_state *context,
BW_VAL_TRACE_COUNT();
- out = dcn30_fast_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel);
+ out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt,
+&vlevel, fast_validate);
if (pipe_cnt == 0)
goto validate_out;
--
2.27.0
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_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 07/10] drm/amd/display: [FW Promotion] Release 0.0.24
2020-07-10 20:33 [PATCH 00/10] DC Patches July 10, 2020 Rodrigo Siqueira
` (5 preceding siblings ...)
2020-07-10 20:33 ` [PATCH 06/10] drm/amd/display: fix dcn3 p_state_change_support validation Rodrigo Siqueira
@ 2020-07-10 20:33 ` Rodrigo Siqueira
2020-07-10 20:33 ` [PATCH 08/10] drm/amd/display: 3.2.94 Rodrigo Siqueira
` (2 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Rodrigo Siqueira @ 2020-07-10 20:33 UTC (permalink / raw)
To: amd-gfx
Cc: Aric Cyr, Eryk.Brol, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, Aurabindo.Pillai, Bhawanpreet.Lakha,
Anthony Koo
From: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index ce96143c402a..513a5f8f817e 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -36,10 +36,10 @@
/* Firmware versioning. */
#ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x5ad38d883
+#define DMUB_FW_VERSION_GIT_HASH 0xf675c6448
#define DMUB_FW_VERSION_MAJOR 0
#define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 23
+#define DMUB_FW_VERSION_REVISION 24
#define DMUB_FW_VERSION_UCODE ((DMUB_FW_VERSION_MAJOR << 24) | (DMUB_FW_VERSION_MINOR << 16) | DMUB_FW_VERSION_REVISION)
#endif
--
2.27.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 08/10] drm/amd/display: 3.2.94
2020-07-10 20:33 [PATCH 00/10] DC Patches July 10, 2020 Rodrigo Siqueira
` (6 preceding siblings ...)
2020-07-10 20:33 ` [PATCH 07/10] drm/amd/display: [FW Promotion] Release 0.0.24 Rodrigo Siqueira
@ 2020-07-10 20:33 ` Rodrigo Siqueira
2020-07-10 20:33 ` [PATCH 09/10] drm/amd/display: Reuse parsing code of debugfs write buffer Rodrigo Siqueira
2020-07-10 20:33 ` Rodrigo Siqueira
9 siblings, 0 replies; 18+ messages in thread
From: Rodrigo Siqueira @ 2020-07-10 20:33 UTC (permalink / raw)
To: amd-gfx
Cc: Aric Cyr, Eryk.Brol, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, Aurabindo.Pillai, Bhawanpreet.Lakha
From: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index c2336ca3a9e0..e5a1a9eb6217 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -42,7 +42,7 @@
#include "inc/hw/dmcu.h"
#include "dml/display_mode_lib.h"
-#define DC_VER "3.2.93"
+#define DC_VER "3.2.94"
#define MAX_SURFACES 3
#define MAX_PLANES 6
--
2.27.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 09/10] drm/amd/display: Reuse parsing code of debugfs write buffer
2020-07-10 20:33 [PATCH 00/10] DC Patches July 10, 2020 Rodrigo Siqueira
` (7 preceding siblings ...)
2020-07-10 20:33 ` [PATCH 08/10] drm/amd/display: 3.2.94 Rodrigo Siqueira
@ 2020-07-10 20:33 ` Rodrigo Siqueira
2020-07-10 20:33 ` Rodrigo Siqueira
9 siblings, 0 replies; 18+ messages in thread
From: Rodrigo Siqueira @ 2020-07-10 20:33 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, Aurabindo.Pillai, Mikita Lipski,
Bhawanpreet.Lakha, Nicholas Kazlauskas
From: Mikita Lipski <mikita.lipski@amd.com>
[why]
Move code for parsing debugfs input into an array of int parameters by
specifying the max number of expected parameters
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 259 +++++++++---------
1 file changed, 128 insertions(+), 131 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index db4fab10a0c4..caf3beaf4b7b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -46,6 +46,89 @@ struct dmub_debugfs_trace_entry {
uint32_t param1;
};
+
+/* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array
+ *
+ * Function takes in attributes passed to debugfs write entry
+ * and writes into param array.
+ * The user passes max_param_num to identify maximum number of
+ * parameters that could be parsed.
+ *
+ */
+static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size,
+ long *param, const char __user *buf,
+ int max_param_num,
+ uint8_t *param_nums)
+{
+ char *wr_buf_ptr = NULL;
+ uint32_t wr_buf_count = 0;
+ int r;
+ char *sub_str = NULL;
+ const char delimiter[3] = {' ', '\n', '\0'};
+ uint8_t param_index = 0;
+
+ *param_nums = 0;
+
+ wr_buf_ptr = wr_buf;
+
+ r = copy_from_user(wr_buf_ptr, buf, wr_buf_size);
+
+ /* r is bytes not be copied */
+ if (r >= wr_buf_size) {
+ DRM_DEBUG_DRIVER("user data not be read\n");
+ return -EINVAL;
+ }
+
+ /* check number of parameters. isspace could not differ space and \n */
+ while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) {
+ /* skip space*/
+ while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
+ wr_buf_ptr++;
+ wr_buf_count++;
+ }
+
+ if (wr_buf_count == wr_buf_size)
+ break;
+
+ /* skip non-space*/
+ while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) {
+ wr_buf_ptr++;
+ wr_buf_count++;
+ }
+
+ (*param_nums)++;
+
+ if (wr_buf_count == wr_buf_size)
+ break;
+ }
+
+ if (*param_nums > max_param_num)
+ *param_nums = max_param_num;
+;
+
+ wr_buf_ptr = wr_buf; /* reset buf pointer */
+ wr_buf_count = 0; /* number of char already checked */
+
+ while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
+ wr_buf_ptr++;
+ wr_buf_count++;
+ }
+
+ while (param_index < *param_nums) {
+ /* after strsep, wr_buf_ptr will be moved to after space */
+ sub_str = strsep(&wr_buf_ptr, delimiter);
+
+ r = kstrtol(sub_str, 16, &(param[param_index]));
+
+ if (r)
+ DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r);
+
+ param_index++;
+ }
+
+ return 0;
+}
+
/* function description
* get/ set DP configuration: lane_count, link_rate, spread_spectrum
*
@@ -161,15 +244,11 @@ static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,
struct dc *dc = (struct dc *)link->dc;
struct dc_link_settings prefer_link_settings;
char *wr_buf = NULL;
- char *wr_buf_ptr = NULL;
const uint32_t wr_buf_size = 40;
- int r;
- int bytes_from_user;
- char *sub_str;
/* 0: lane_count; 1: link_rate */
- uint8_t param_index = 0;
+ int max_param_num = 2;
+ uint8_t param_nums = 0;
long param[2];
- const char delimiter[3] = {' ', '\n', '\0'};
bool valid_input = false;
if (size == 0)
@@ -177,35 +256,20 @@ static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,
wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
if (!wr_buf)
- return -EINVAL;
- wr_buf_ptr = wr_buf;
+ return -ENOSPC;
- r = copy_from_user(wr_buf_ptr, buf, wr_buf_size);
-
- /* r is bytes not be copied */
- if (r >= wr_buf_size) {
+ if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
+ (long *)param, buf,
+ max_param_num,
+ ¶m_nums)) {
kfree(wr_buf);
- DRM_DEBUG_DRIVER("user data not read\n");
return -EINVAL;
}
- bytes_from_user = wr_buf_size - r;
-
- while (isspace(*wr_buf_ptr))
- wr_buf_ptr++;
-
- while ((*wr_buf_ptr != '\0') && (param_index < 2)) {
-
- sub_str = strsep(&wr_buf_ptr, delimiter);
-
- r = kstrtol(sub_str, 16, ¶m[param_index]);
-
- if (r)
- DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r);
-
- param_index++;
- while (isspace(*wr_buf_ptr))
- wr_buf_ptr++;
+ if (param_nums <= 0) {
+ kfree(wr_buf);
+ DRM_DEBUG_DRIVER("user data not be read\n");
+ return -EINVAL;
}
switch (param[0]) {
@@ -233,7 +297,7 @@ static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,
if (!valid_input) {
kfree(wr_buf);
DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
- return bytes_from_user;
+ return size;
}
/* save user force lane_count, link_rate to preferred settings
@@ -246,7 +310,7 @@ static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,
dc_link_set_preferred_link_settings(dc, &prefer_link_settings, link);
kfree(wr_buf);
- return bytes_from_user;
+ return size;
}
/* function: get current DP PHY settings: voltage swing, pre-emphasis,
@@ -337,51 +401,34 @@ static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
struct dc_link *link = connector->dc_link;
struct dc *dc = (struct dc *)link->dc;
char *wr_buf = NULL;
- char *wr_buf_ptr = NULL;
uint32_t wr_buf_size = 40;
- int r;
- int bytes_from_user;
- char *sub_str;
- uint8_t param_index = 0;
long param[3];
- const char delimiter[3] = {' ', '\n', '\0'};
bool use_prefer_link_setting;
struct link_training_settings link_lane_settings;
+ int max_param_num = 3;
+ uint8_t param_nums = 0;
+ int r = 0;
+
if (size == 0)
- return 0;
+ return -EINVAL;
wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
if (!wr_buf)
- return 0;
- wr_buf_ptr = wr_buf;
+ return -ENOSPC;
- r = copy_from_user(wr_buf_ptr, buf, wr_buf_size);
-
- /* r is bytes not be copied */
- if (r >= wr_buf_size) {
+ if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
+ (long *)param, buf,
+ max_param_num,
+ ¶m_nums)) {
kfree(wr_buf);
- DRM_DEBUG_DRIVER("user data not be read\n");
- return 0;
+ return -EINVAL;
}
- bytes_from_user = wr_buf_size - r;
-
- while (isspace(*wr_buf_ptr))
- wr_buf_ptr++;
-
- while ((*wr_buf_ptr != '\0') && (param_index < 3)) {
-
- sub_str = strsep(&wr_buf_ptr, delimiter);
-
- r = kstrtol(sub_str, 16, ¶m[param_index]);
-
- if (r)
- DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r);
-
- param_index++;
- while (isspace(*wr_buf_ptr))
- wr_buf_ptr++;
+ if (param_nums <= 0) {
+ kfree(wr_buf);
+ DRM_DEBUG_DRIVER("user data not be read\n");
+ return -EINVAL;
}
if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) ||
@@ -389,7 +436,7 @@ static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
(param[2] > POST_CURSOR2_MAX_LEVEL)) {
kfree(wr_buf);
DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n");
- return bytes_from_user;
+ return size;
}
/* get link settings: lane count, link rate */
@@ -429,7 +476,7 @@ static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
dc_link_set_drive_settings(dc, &link_lane_settings, link);
kfree(wr_buf);
- return bytes_from_user;
+ return size;
}
/* function description
@@ -496,19 +543,13 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us
struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
struct dc_link *link = connector->dc_link;
char *wr_buf = NULL;
- char *wr_buf_ptr = NULL;
uint32_t wr_buf_size = 100;
- uint32_t wr_buf_count = 0;
- int r;
- int bytes_from_user;
- char *sub_str = NULL;
- uint8_t param_index = 0;
- uint8_t param_nums = 0;
long param[11] = {0x0};
- const char delimiter[3] = {' ', '\n', '\0'};
+ int max_param_num = 11;
enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
bool disable_hpd = false;
bool valid_test_pattern = false;
+ uint8_t param_nums = 0;
/* init with defalut 80bit custom pattern */
uint8_t custom_pattern[10] = {
0x1f, 0x7c, 0xf0, 0xc1, 0x07,
@@ -522,70 +563,26 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us
int i;
if (size == 0)
- return 0;
+ return -EINVAL;
wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
if (!wr_buf)
- return 0;
- wr_buf_ptr = wr_buf;
+ return -ENOSPC;
- r = copy_from_user(wr_buf_ptr, buf, wr_buf_size);
-
- /* r is bytes not be copied */
- if (r >= wr_buf_size) {
+ if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
+ (long *)param, buf,
+ max_param_num,
+ ¶m_nums)) {
kfree(wr_buf);
- DRM_DEBUG_DRIVER("user data not be read\n");
- return 0;
- }
-
- bytes_from_user = wr_buf_size - r;
-
- /* check number of parameters. isspace could not differ space and \n */
- while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) {
- /* skip space*/
- while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
- wr_buf_ptr++;
- wr_buf_count++;
- }
-
- if (wr_buf_count == wr_buf_size)
- break;
-
- /* skip non-space*/
- while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) {
- wr_buf_ptr++;
- wr_buf_count++;
- }
-
- param_nums++;
-
- if (wr_buf_count == wr_buf_size)
- break;
+ return -EINVAL;
}
- /* max 11 parameters */
- if (param_nums > 11)
- param_nums = 11;
-
- wr_buf_ptr = wr_buf; /* reset buf pinter */
- wr_buf_count = 0; /* number of char already checked */
-
- while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
- wr_buf_ptr++;
- wr_buf_count++;
+ if (param_nums <= 0) {
+ kfree(wr_buf);
+ DRM_DEBUG_DRIVER("user data not be read\n");
+ return -EINVAL;
}
- while (param_index < param_nums) {
- /* after strsep, wr_buf_ptr will be moved to after space */
- sub_str = strsep(&wr_buf_ptr, delimiter);
-
- r = kstrtol(sub_str, 16, ¶m[param_index]);
-
- if (r)
- DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r);
-
- param_index++;
- }
test_pattern = param[0];
@@ -618,7 +615,7 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us
if (!valid_test_pattern) {
kfree(wr_buf);
DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n");
- return bytes_from_user;
+ return size;
}
if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
@@ -685,7 +682,7 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us
kfree(wr_buf);
- return bytes_from_user;
+ return size;
}
/**
--
2.27.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 10/10] drm/amd/display: handle failed allocation during stream construction
2020-07-10 20:33 [PATCH 00/10] DC Patches July 10, 2020 Rodrigo Siqueira
@ 2020-07-10 20:33 ` Rodrigo Siqueira
2020-07-10 20:33 ` [PATCH 02/10] drm/amd/display: Power down hardware if set mode is not called before timeout Rodrigo Siqueira
` (8 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Rodrigo Siqueira @ 2020-07-10 20:33 UTC (permalink / raw)
To: amd-gfx
Cc: Josip Pavic, Eryk.Brol, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, Aric Cyr, stable, Aurabindo.Pillai,
Bhawanpreet.Lakha
From: Josip Pavic <Josip.Pavic@amd.com>
[Why]
Failing to allocate a transfer function during stream construction leads
to a null pointer dereference
[How]
Handle the failed allocation by failing the stream construction
Cc: stable@vger.kernel.org
Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_stream.c | 19 ++++++++++++++++---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 3b897372ed27..d6989d115c5c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -56,7 +56,7 @@ void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink)
}
}
-static void dc_stream_construct(struct dc_stream_state *stream,
+static bool dc_stream_construct(struct dc_stream_state *stream,
struct dc_sink *dc_sink_data)
{
uint32_t i = 0;
@@ -118,11 +118,17 @@ static void dc_stream_construct(struct dc_stream_state *stream,
update_stream_signal(stream, dc_sink_data);
stream->out_transfer_func = dc_create_transfer_func();
+ if (stream->out_transfer_func == NULL) {
+ dc_sink_release(dc_sink_data);
+ return false;
+ }
stream->out_transfer_func->type = TF_TYPE_BYPASS;
stream->out_transfer_func->ctx = stream->ctx;
stream->stream_id = stream->ctx->dc_stream_id_count;
stream->ctx->dc_stream_id_count++;
+
+ return true;
}
static void dc_stream_destruct(struct dc_stream_state *stream)
@@ -164,13 +170,20 @@ struct dc_stream_state *dc_create_stream_for_sink(
stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL);
if (stream == NULL)
- return NULL;
+ goto alloc_fail;
- dc_stream_construct(stream, sink);
+ if (dc_stream_construct(stream, sink) == false)
+ goto construct_fail;
kref_init(&stream->refcount);
return stream;
+
+construct_fail:
+ kfree(stream);
+
+alloc_fail:
+ return NULL;
}
struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream)
--
2.27.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 10/10] drm/amd/display: handle failed allocation during stream construction
@ 2020-07-10 20:33 ` Rodrigo Siqueira
0 siblings, 0 replies; 18+ messages in thread
From: Rodrigo Siqueira @ 2020-07-10 20:33 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, Eryk.Brol, Josip Pavic, stable,
Aric Cyr
From: Josip Pavic <Josip.Pavic@amd.com>
[Why]
Failing to allocate a transfer function during stream construction leads
to a null pointer dereference
[How]
Handle the failed allocation by failing the stream construction
Cc: stable@vger.kernel.org
Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_stream.c | 19 ++++++++++++++++---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 3b897372ed27..d6989d115c5c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -56,7 +56,7 @@ void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink)
}
}
-static void dc_stream_construct(struct dc_stream_state *stream,
+static bool dc_stream_construct(struct dc_stream_state *stream,
struct dc_sink *dc_sink_data)
{
uint32_t i = 0;
@@ -118,11 +118,17 @@ static void dc_stream_construct(struct dc_stream_state *stream,
update_stream_signal(stream, dc_sink_data);
stream->out_transfer_func = dc_create_transfer_func();
+ if (stream->out_transfer_func == NULL) {
+ dc_sink_release(dc_sink_data);
+ return false;
+ }
stream->out_transfer_func->type = TF_TYPE_BYPASS;
stream->out_transfer_func->ctx = stream->ctx;
stream->stream_id = stream->ctx->dc_stream_id_count;
stream->ctx->dc_stream_id_count++;
+
+ return true;
}
static void dc_stream_destruct(struct dc_stream_state *stream)
@@ -164,13 +170,20 @@ struct dc_stream_state *dc_create_stream_for_sink(
stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL);
if (stream == NULL)
- return NULL;
+ goto alloc_fail;
- dc_stream_construct(stream, sink);
+ if (dc_stream_construct(stream, sink) == false)
+ goto construct_fail;
kref_init(&stream->refcount);
return stream;
+
+construct_fail:
+ kfree(stream);
+
+alloc_fail:
+ return NULL;
}
struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream)
--
2.27.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 10/10] drm/amd/display: handle failed allocation during stream construction
2020-07-10 20:33 ` Rodrigo Siqueira
@ 2020-07-16 0:27 ` Sasha Levin
-1 siblings, 0 replies; 18+ messages in thread
From: Sasha Levin @ 2020-07-16 0:27 UTC (permalink / raw)
To: Sasha Levin, Rodrigo Siqueira, Josip Pavic, amd-gfx
Cc: Sunpeng.Li, Harry.Wentland, stable
Hi
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.7.8, v5.4.51, v4.19.132, v4.14.188, v4.9.230, v4.4.230.
v5.7.8: Build OK!
v5.4.51: Failed to apply! Possible dependencies:
d9e32672a1285 ("drm/amd/display: cleanup of construct and destruct funcs")
v4.19.132: Failed to apply! Possible dependencies:
0e3d73f1a440e ("drm/amd/display: Add Raven2 definitions in dc")
1e7e86c43f38d ("drm/amd/display: decouple front and backend pgm using dpms_off as backend enable flag")
21e471f0850de ("drm/amd/display: Set dispclk and dprefclock directly")
24f7dd7ea98dc ("drm/amd/display: move pplib/smu notification to dccg block")
4e60536d093f4 ("drm/amd/display: Set DFS bypass flags for dce110")
5a83c93249098 ("drm/amd/display: Add support for toggling DFS bypass")
76d981a9fe823 ("Revert "drm/amd/display: make clk_mgr call enable_pme_wa"")
7ed4e6352c16f ("drm/amd/display: Add DCN2 HW Sequencer and Resource")
84e7fc05a9270 ("drm/amd/display: rename dccg to clk_mgr")
8c3db1284a016 ("drm/amdgpu: fill in amdgpu_dm_remove_sink_from_freesync_module")
98e6436d3af5f ("drm/amd/display: Refactor FreeSync module")
ad908423ef86f ("drm/amd/display: support 48 MHZ refclk off")
d9673c920c035 ("drm/amd/display: Pass init_data into DCN resource creation")
d9e32672a1285 ("drm/amd/display: cleanup of construct and destruct funcs")
v4.14.188: Failed to apply! Possible dependencies:
1b0c0f9dc5ca6 ("drm/amdgpu: move userptr BOs to CPU domain during CS v2")
1ed3d2567c800 ("drm/amdgpu: keep the MMU lock until the update ends v4")
3fe89771cb0a6 ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
4562236b3bc0a ("drm/amd/dc: Add dc display driver (v2)")
60de1c1740f39 ("drm/amdgpu: use a rw_semaphore for MMU notifiers")
9a18999640fa6 ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
9cca0b8e5df0a ("drm/amdgpu: move amdgpu_cs_sysvm_access_required into find_mapping")
a216ab09955d6 ("drm/amdgpu: fix userptr put_page handling")
b72cf4fca2bb7 ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
ca666a3c298f8 ("drm/amdgpu: stop using BO status for user pages")
v4.9.230: Failed to apply! Possible dependencies:
1cec20f0ea0e3 ("dma-buf: Restart reservation_object_wait_timeout_rcu() after writes")
3fe89771cb0a6 ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
4562236b3bc0a ("drm/amd/dc: Add dc display driver (v2)")
4df654d293c64 ("drm/amdgpu: move amdgpu_uvd structure to uvd header")
5e5681788befb ("drm/amdgpu: move amdgpu_vce structure to vce header")
660e855813f78 ("amdgpu: use drm sync objects for shared semaphores (v6)")
78010cd9736ec ("dma-buf/fence: add an lockdep_assert_held()")
95aa13f6b196d ("drm/amdgpu: move amdgpu_vcn structure to vcn header")
95d0906f85065 ("drm/amdgpu: add initial vcn support and decode tests")
9a18999640fa6 ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
b636922553ee2 ("drm/amdgpu: only move VM BOs in the LRU during validation v2")
b72cf4fca2bb7 ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
f54d1867005c3 ("dma-buf: Rename struct fence to dma_fence")
fedf54132d241 ("dma-buf: Restart reservation_object_get_fences_rcu() after writes")
v4.4.230: Failed to apply! Possible dependencies:
1f7371b2a5faf ("drm/amd/powerplay: add basic powerplay framework")
288912cb95d15 ("drm/amdgpu: use $(src) in Makefile (v2)")
37cd0ca204a55 ("drm/amdgpu: unify AMDGPU_CTX_MAX_CS_PENDING and amdgpu_sched_jobs")
3c0eea6c35d93 ("drm/amdgpu: put VM page tables directly into duplicates list")
3f99dd814a6fd ("drm/amdgpu: save and restore UVD context with suspend and resume")
4325198180e5a ("drm/amdgpu: remove GART page addr array")
4562236b3bc0a ("drm/amd/dc: Add dc display driver (v2)")
4acabfe3793eb ("drm/amdgpu: fix num_ibs check")
4df654d293c64 ("drm/amdgpu: move amdgpu_uvd structure to uvd header")
50838c8cc413d ("drm/amdgpu: add proper job alloc/free functions")
56467ebfb2548 ("drm/amdgpu: split VM PD and PT handling during CS")
5e5681788befb ("drm/amdgpu: move amdgpu_vce structure to vce header")
7270f8391df1a ("drm/amdgpu: add amdgpu_set_ib_value helper (v2)")
95aa13f6b196d ("drm/amdgpu: move amdgpu_vcn structure to vcn header")
9a18999640fa6 ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
a1d29476d666f ("drm/amdgpu: optionally enable GART debugfs file")
a8fe58cec351c ("drm/amd: add ACP driver support")
c036554170fcc ("drm/amdgpu: handle more than 10 UVD sessions (v2)")
c3cca41e6249e ("drm/amdgpu: cleanup amdgpu_cs_parser structure")
cadf97b196a1e ("drm/amdgpu: clean up non-scheduler code path (v2)")
cd75dc6887f1e ("drm/amdgpu: separate pushing CS to scheduler")
d71518b5aa7c9 ("drm/amdgpu: cleanup in kernel job submission")
d7af97dbccf01 ("drm/amdgpu: send UVD IB tests directly to the ring again")
d8e0cae645504 ("drm/amdgpu: validate duplicates first")
f69f90a113f28 ("drm/amdgpu: fix amdgpu_cs_get_threshold_for_moves handling")
fdba11f4079ec ("drm/amdgpu: move all Kconfig options to amdgpu/Kconfig")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks
Sasha
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 10/10] drm/amd/display: handle failed allocation during stream construction
@ 2020-07-16 0:27 ` Sasha Levin
0 siblings, 0 replies; 18+ messages in thread
From: Sasha Levin @ 2020-07-16 0:27 UTC (permalink / raw)
To: Sasha Levin, Rodrigo Siqueira, Josip Pavic, amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, stable, stable
Hi
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.7.8, v5.4.51, v4.19.132, v4.14.188, v4.9.230, v4.4.230.
v5.7.8: Build OK!
v5.4.51: Failed to apply! Possible dependencies:
d9e32672a1285 ("drm/amd/display: cleanup of construct and destruct funcs")
v4.19.132: Failed to apply! Possible dependencies:
0e3d73f1a440e ("drm/amd/display: Add Raven2 definitions in dc")
1e7e86c43f38d ("drm/amd/display: decouple front and backend pgm using dpms_off as backend enable flag")
21e471f0850de ("drm/amd/display: Set dispclk and dprefclock directly")
24f7dd7ea98dc ("drm/amd/display: move pplib/smu notification to dccg block")
4e60536d093f4 ("drm/amd/display: Set DFS bypass flags for dce110")
5a83c93249098 ("drm/amd/display: Add support for toggling DFS bypass")
76d981a9fe823 ("Revert "drm/amd/display: make clk_mgr call enable_pme_wa"")
7ed4e6352c16f ("drm/amd/display: Add DCN2 HW Sequencer and Resource")
84e7fc05a9270 ("drm/amd/display: rename dccg to clk_mgr")
8c3db1284a016 ("drm/amdgpu: fill in amdgpu_dm_remove_sink_from_freesync_module")
98e6436d3af5f ("drm/amd/display: Refactor FreeSync module")
ad908423ef86f ("drm/amd/display: support 48 MHZ refclk off")
d9673c920c035 ("drm/amd/display: Pass init_data into DCN resource creation")
d9e32672a1285 ("drm/amd/display: cleanup of construct and destruct funcs")
v4.14.188: Failed to apply! Possible dependencies:
1b0c0f9dc5ca6 ("drm/amdgpu: move userptr BOs to CPU domain during CS v2")
1ed3d2567c800 ("drm/amdgpu: keep the MMU lock until the update ends v4")
3fe89771cb0a6 ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
4562236b3bc0a ("drm/amd/dc: Add dc display driver (v2)")
60de1c1740f39 ("drm/amdgpu: use a rw_semaphore for MMU notifiers")
9a18999640fa6 ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
9cca0b8e5df0a ("drm/amdgpu: move amdgpu_cs_sysvm_access_required into find_mapping")
a216ab09955d6 ("drm/amdgpu: fix userptr put_page handling")
b72cf4fca2bb7 ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
ca666a3c298f8 ("drm/amdgpu: stop using BO status for user pages")
v4.9.230: Failed to apply! Possible dependencies:
1cec20f0ea0e3 ("dma-buf: Restart reservation_object_wait_timeout_rcu() after writes")
3fe89771cb0a6 ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
4562236b3bc0a ("drm/amd/dc: Add dc display driver (v2)")
4df654d293c64 ("drm/amdgpu: move amdgpu_uvd structure to uvd header")
5e5681788befb ("drm/amdgpu: move amdgpu_vce structure to vce header")
660e855813f78 ("amdgpu: use drm sync objects for shared semaphores (v6)")
78010cd9736ec ("dma-buf/fence: add an lockdep_assert_held()")
95aa13f6b196d ("drm/amdgpu: move amdgpu_vcn structure to vcn header")
95d0906f85065 ("drm/amdgpu: add initial vcn support and decode tests")
9a18999640fa6 ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
b636922553ee2 ("drm/amdgpu: only move VM BOs in the LRU during validation v2")
b72cf4fca2bb7 ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
f54d1867005c3 ("dma-buf: Rename struct fence to dma_fence")
fedf54132d241 ("dma-buf: Restart reservation_object_get_fences_rcu() after writes")
v4.4.230: Failed to apply! Possible dependencies:
1f7371b2a5faf ("drm/amd/powerplay: add basic powerplay framework")
288912cb95d15 ("drm/amdgpu: use $(src) in Makefile (v2)")
37cd0ca204a55 ("drm/amdgpu: unify AMDGPU_CTX_MAX_CS_PENDING and amdgpu_sched_jobs")
3c0eea6c35d93 ("drm/amdgpu: put VM page tables directly into duplicates list")
3f99dd814a6fd ("drm/amdgpu: save and restore UVD context with suspend and resume")
4325198180e5a ("drm/amdgpu: remove GART page addr array")
4562236b3bc0a ("drm/amd/dc: Add dc display driver (v2)")
4acabfe3793eb ("drm/amdgpu: fix num_ibs check")
4df654d293c64 ("drm/amdgpu: move amdgpu_uvd structure to uvd header")
50838c8cc413d ("drm/amdgpu: add proper job alloc/free functions")
56467ebfb2548 ("drm/amdgpu: split VM PD and PT handling during CS")
5e5681788befb ("drm/amdgpu: move amdgpu_vce structure to vce header")
7270f8391df1a ("drm/amdgpu: add amdgpu_set_ib_value helper (v2)")
95aa13f6b196d ("drm/amdgpu: move amdgpu_vcn structure to vcn header")
9a18999640fa6 ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
a1d29476d666f ("drm/amdgpu: optionally enable GART debugfs file")
a8fe58cec351c ("drm/amd: add ACP driver support")
c036554170fcc ("drm/amdgpu: handle more than 10 UVD sessions (v2)")
c3cca41e6249e ("drm/amdgpu: cleanup amdgpu_cs_parser structure")
cadf97b196a1e ("drm/amdgpu: clean up non-scheduler code path (v2)")
cd75dc6887f1e ("drm/amdgpu: separate pushing CS to scheduler")
d71518b5aa7c9 ("drm/amdgpu: cleanup in kernel job submission")
d7af97dbccf01 ("drm/amdgpu: send UVD IB tests directly to the ring again")
d8e0cae645504 ("drm/amdgpu: validate duplicates first")
f69f90a113f28 ("drm/amdgpu: fix amdgpu_cs_get_threshold_for_moves handling")
fdba11f4079ec ("drm/amdgpu: move all Kconfig options to amdgpu/Kconfig")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks
Sasha
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