From: kernel test robot <lkp@intel.com>
To: Jack Zhang <Jack.Zhang1@amd.com>
Cc: Leo Liu <leo.liu@amd.com>,
kbuild-all@lists.01.org, dri-devel@lists.freedesktop.org
Subject: [radeon-alex:amd-staging-drm-next 1066/1110] drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c:1233:3: warning: variable 'direct_poll' set but not used
Date: Fri, 17 Jul 2020 09:26:58 +0800 [thread overview]
Message-ID: <202007170954.9O7P4AwW%lkp@intel.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 13547 bytes --]
tree: git://people.freedesktop.org/~agd5f/linux.git amd-staging-drm-next
head: cefd5db37208da458fa10f83f866f2f37eef70e9
commit: 4a33206e976be79b832d5a826565b5cb430de877 [1066/1110] drm/amd/sriov porting sriov cap to vcn3.0
config: parisc-randconfig-r015-20200717 (attached as .config)
compiler: hppa-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout 4a33206e976be79b832d5a826565b5cb430de877
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=parisc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
In file included from include/linux/mm.h:94,
from include/drm/drm_vma_manager.h:27,
from include/drm/drm_gem.h:40,
from include/drm/ttm/ttm_bo_api.h:34,
from drivers/gpu/drm/amd/amdgpu/amdgpu.h:53,
from drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c:25:
include/asm-generic/pgtable.h: In function 'pte_clear_not_present_full':
arch/parisc/include/asm/pgtable.h:96:9: warning: variable 'old_pte' set but not used [-Wunused-but-set-variable]
96 | pte_t old_pte; \
| ^~~~~~~
arch/parisc/include/asm/pgtable.h:322:34: note: in expansion of macro 'set_pte_at'
322 | #define pte_clear(mm, addr, xp) set_pte_at(mm, addr, xp, __pte(0))
| ^~~~~~~~~~
include/asm-generic/pgtable.h:201:2: note: in expansion of macro 'pte_clear'
201 | pte_clear(mm, address, ptep);
| ^~~~~~~~~
include/asm-generic/pgtable.h: In function '__ptep_modify_prot_commit':
arch/parisc/include/asm/pgtable.h:96:9: warning: variable 'old_pte' set but not used [-Wunused-but-set-variable]
96 | pte_t old_pte; \
| ^~~~~~~
include/asm-generic/pgtable.h:640:2: note: in expansion of macro 'set_pte_at'
640 | set_pte_at(vma->vm_mm, addr, ptep, pte);
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c: In function 'vcn_v3_0_start_sriov':
>> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c:1233:3: warning: variable 'direct_poll' set but not used [-Wunused-but-set-variable]
1233 | direct_poll = { {0} };
| ^~~~~~~~~~~
In file included from drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c:25:
At top level:
drivers/gpu/drm/amd/amdgpu/amdgpu.h:192:19: warning: 'debug_evictions' defined but not used [-Wunused-const-variable=]
192 | static const bool debug_evictions; /* = false */
| ^~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/amdgpu.h:191:18: warning: 'sched_policy' defined but not used [-Wunused-const-variable=]
191 | static const int sched_policy = KFD_SCHED_POLICY_HWS;
| ^~~~~~~~~~~~
In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dc_types.h:33,
from drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services_types.h:30,
from drivers/gpu/drm/amd/amdgpu/../include/dm_pp_interface.h:26,
from drivers/gpu/drm/amd/amdgpu/amdgpu.h:65,
from drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c:25:
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:76:32: warning: 'dc_fixpt_ln2_div_2' defined but not used [-Wunused-const-variable=]
76 | static const struct fixed31_32 dc_fixpt_ln2_div_2 = { 1488522236LL };
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:75:32: warning: 'dc_fixpt_ln2' defined but not used [-Wunused-const-variable=]
75 | static const struct fixed31_32 dc_fixpt_ln2 = { 2977044471LL };
| ^~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:74:32: warning: 'dc_fixpt_e' defined but not used [-Wunused-const-variable=]
74 | static const struct fixed31_32 dc_fixpt_e = { 11674931555LL };
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:73:32: warning: 'dc_fixpt_two_pi' defined but not used [-Wunused-const-variable=]
73 | static const struct fixed31_32 dc_fixpt_two_pi = { 26986075409LL };
| ^~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:72:32: warning: 'dc_fixpt_pi' defined but not used [-Wunused-const-variable=]
72 | static const struct fixed31_32 dc_fixpt_pi = { 13493037705LL };
| ^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:67:32: warning: 'dc_fixpt_zero' defined but not used [-Wunused-const-variable=]
67 | static const struct fixed31_32 dc_fixpt_zero = { 0 };
| ^~~~~~~~~~~~~
vim +/direct_poll +1233 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1210
1211 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)
1212 {
1213 int i, j;
1214 struct amdgpu_ring *ring;
1215 uint64_t cache_addr;
1216 uint64_t rb_addr;
1217 uint64_t ctx_addr;
1218 uint32_t param, resp, expected;
1219 uint32_t offset, cache_size;
1220 uint32_t tmp, timeout;
1221 uint32_t id;
1222
1223 struct amdgpu_mm_table *table = &adev->virt.mm_table;
1224 uint32_t *table_loc;
1225 uint32_t table_size;
1226 uint32_t size, size_dw;
1227
1228 struct mmsch_v3_0_cmd_direct_write
1229 direct_wt = { {0} };
1230 struct mmsch_v3_0_cmd_direct_read_modify_write
1231 direct_rd_mod_wt = { {0} };
1232 struct mmsch_v3_0_cmd_direct_polling
> 1233 direct_poll = { {0} };
1234 struct mmsch_v3_0_cmd_end end = { {0} };
1235 struct mmsch_v3_0_init_header header;
1236
1237 direct_wt.cmd_header.command_type =
1238 MMSCH_COMMAND__DIRECT_REG_WRITE;
1239 direct_rd_mod_wt.cmd_header.command_type =
1240 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1241 direct_poll.cmd_header.command_type =
1242 MMSCH_COMMAND__DIRECT_REG_POLLING;
1243 end.cmd_header.command_type =
1244 MMSCH_COMMAND__END;
1245
1246 header.version = MMSCH_VERSION;
1247 header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2;
1248 for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) {
1249 header.inst[i].init_status = 0;
1250 header.inst[i].table_offset = 0;
1251 header.inst[i].table_size = 0;
1252 }
1253
1254 table_loc = (uint32_t *)table->cpu_addr;
1255 table_loc += header.total_size;
1256 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1257 if (adev->vcn.harvest_config & (1 << i))
1258 continue;
1259
1260 table_size = 0;
1261
1262 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i,
1263 mmUVD_STATUS),
1264 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
1265
1266 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
1267
1268 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1269 id = amdgpu_ucode_id_vcns[i];
1270 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1271 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1272 adev->firmware.ucode[id].tmr_mc_addr_lo);
1273 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1274 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1275 adev->firmware.ucode[id].tmr_mc_addr_hi);
1276 offset = 0;
1277 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1278 mmUVD_VCPU_CACHE_OFFSET0),
1279 0);
1280 } else {
1281 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1282 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1283 lower_32_bits(adev->vcn.inst[i].gpu_addr));
1284 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1285 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1286 upper_32_bits(adev->vcn.inst[i].gpu_addr));
1287 offset = cache_size;
1288 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1289 mmUVD_VCPU_CACHE_OFFSET0),
1290 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
1291 }
1292
1293 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1294 mmUVD_VCPU_CACHE_SIZE0),
1295 cache_size);
1296
1297 cache_addr = adev->vcn.inst[i].gpu_addr + offset;
1298 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1299 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1300 lower_32_bits(cache_addr));
1301 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1302 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1303 upper_32_bits(cache_addr));
1304 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1305 mmUVD_VCPU_CACHE_OFFSET1),
1306 0);
1307 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1308 mmUVD_VCPU_CACHE_SIZE1),
1309 AMDGPU_VCN_STACK_SIZE);
1310
1311 cache_addr = adev->vcn.inst[i].gpu_addr + offset +
1312 AMDGPU_VCN_STACK_SIZE;
1313 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1314 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1315 lower_32_bits(cache_addr));
1316 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1317 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1318 upper_32_bits(cache_addr));
1319 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1320 mmUVD_VCPU_CACHE_OFFSET2),
1321 0);
1322 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1323 mmUVD_VCPU_CACHE_SIZE2),
1324 AMDGPU_VCN_CONTEXT_SIZE);
1325
1326 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
1327 ring = &adev->vcn.inst[i].ring_enc[j];
1328 ring->wptr = 0;
1329 rb_addr = ring->gpu_addr;
1330 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1331 mmUVD_RB_BASE_LO),
1332 lower_32_bits(rb_addr));
1333 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1334 mmUVD_RB_BASE_HI),
1335 upper_32_bits(rb_addr));
1336 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1337 mmUVD_RB_SIZE),
1338 ring->ring_size / 4);
1339 }
1340
1341 ring = &adev->vcn.inst[i].ring_dec;
1342 ring->wptr = 0;
1343 rb_addr = ring->gpu_addr;
1344 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1345 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
1346 lower_32_bits(rb_addr));
1347 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1348 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
1349 upper_32_bits(rb_addr));
1350 /* force RBC into idle state */
1351 tmp = order_base_2(ring->ring_size);
1352 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);
1353 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1354 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1355 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1356 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1357 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1358 mmUVD_RBC_RB_CNTL),
1359 tmp);
1360
1361 /* add end packet */
1362 MMSCH_V3_0_INSERT_END();
1363
1364 /* refine header */
1365 header.inst[i].init_status = 1;
1366 header.inst[i].table_offset = header.total_size;
1367 header.inst[i].table_size = table_size;
1368 header.total_size += table_size;
1369 }
1370
1371 /* Update init table header in memory */
1372 size = sizeof(struct mmsch_v3_0_init_header);
1373 table_loc = (uint32_t *)table->cpu_addr;
1374 memcpy((void *)table_loc, &header, size);
1375
1376 /* message MMSCH (in VCN[0]) to initialize this client
1377 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
1378 * of memory descriptor location
1379 */
1380 ctx_addr = table->gpu_addr;
1381 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
1382 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));
1383
1384 /* 2, update vmid of descriptor */
1385 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID);
1386 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1387 /* use domain0 for MM scheduler */
1388 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1389 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp);
1390
1391 /* 3, notify mmsch about the size of this descriptor */
1392 size = header.total_size;
1393 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size);
1394
1395 /* 4, set resp to zero */
1396 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
1397
1398 /* 5, kick off the initialization and wait until
1399 * MMSCH_VF_MAILBOX_RESP becomes non-zero
1400 */
1401 param = 0x10000001;
1402 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param);
1403 tmp = 0;
1404 timeout = 1000;
1405 resp = 0;
1406 expected = param + 1;
1407 while (resp != expected) {
1408 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);
1409 if (resp == expected)
1410 break;
1411
1412 udelay(10);
1413 tmp = tmp + 10;
1414 if (tmp >= timeout) {
1415 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
1416 " waiting for mmMMSCH_VF_MAILBOX_RESP "\
1417 "(expected=0x%08x, readback=0x%08x)\n",
1418 tmp, expected, resp);
1419 return -EBUSY;
1420 }
1421 }
1422
1423 return 0;
1424 }
1425
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 25012 bytes --]
[-- Attachment #3: Type: text/plain, Size: 160 bytes --]
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: kernel test robot <lkp@intel.com>
To: kbuild-all@lists.01.org
Subject: [radeon-alex:amd-staging-drm-next 1066/1110] drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c:1233:3: warning: variable 'direct_poll' set but not used
Date: Fri, 17 Jul 2020 09:26:58 +0800 [thread overview]
Message-ID: <202007170954.9O7P4AwW%lkp@intel.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 13847 bytes --]
tree: git://people.freedesktop.org/~agd5f/linux.git amd-staging-drm-next
head: cefd5db37208da458fa10f83f866f2f37eef70e9
commit: 4a33206e976be79b832d5a826565b5cb430de877 [1066/1110] drm/amd/sriov porting sriov cap to vcn3.0
config: parisc-randconfig-r015-20200717 (attached as .config)
compiler: hppa-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout 4a33206e976be79b832d5a826565b5cb430de877
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=parisc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
In file included from include/linux/mm.h:94,
from include/drm/drm_vma_manager.h:27,
from include/drm/drm_gem.h:40,
from include/drm/ttm/ttm_bo_api.h:34,
from drivers/gpu/drm/amd/amdgpu/amdgpu.h:53,
from drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c:25:
include/asm-generic/pgtable.h: In function 'pte_clear_not_present_full':
arch/parisc/include/asm/pgtable.h:96:9: warning: variable 'old_pte' set but not used [-Wunused-but-set-variable]
96 | pte_t old_pte; \
| ^~~~~~~
arch/parisc/include/asm/pgtable.h:322:34: note: in expansion of macro 'set_pte_at'
322 | #define pte_clear(mm, addr, xp) set_pte_at(mm, addr, xp, __pte(0))
| ^~~~~~~~~~
include/asm-generic/pgtable.h:201:2: note: in expansion of macro 'pte_clear'
201 | pte_clear(mm, address, ptep);
| ^~~~~~~~~
include/asm-generic/pgtable.h: In function '__ptep_modify_prot_commit':
arch/parisc/include/asm/pgtable.h:96:9: warning: variable 'old_pte' set but not used [-Wunused-but-set-variable]
96 | pte_t old_pte; \
| ^~~~~~~
include/asm-generic/pgtable.h:640:2: note: in expansion of macro 'set_pte_at'
640 | set_pte_at(vma->vm_mm, addr, ptep, pte);
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c: In function 'vcn_v3_0_start_sriov':
>> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c:1233:3: warning: variable 'direct_poll' set but not used [-Wunused-but-set-variable]
1233 | direct_poll = { {0} };
| ^~~~~~~~~~~
In file included from drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c:25:
At top level:
drivers/gpu/drm/amd/amdgpu/amdgpu.h:192:19: warning: 'debug_evictions' defined but not used [-Wunused-const-variable=]
192 | static const bool debug_evictions; /* = false */
| ^~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/amdgpu.h:191:18: warning: 'sched_policy' defined but not used [-Wunused-const-variable=]
191 | static const int sched_policy = KFD_SCHED_POLICY_HWS;
| ^~~~~~~~~~~~
In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dc_types.h:33,
from drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services_types.h:30,
from drivers/gpu/drm/amd/amdgpu/../include/dm_pp_interface.h:26,
from drivers/gpu/drm/amd/amdgpu/amdgpu.h:65,
from drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c:25:
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:76:32: warning: 'dc_fixpt_ln2_div_2' defined but not used [-Wunused-const-variable=]
76 | static const struct fixed31_32 dc_fixpt_ln2_div_2 = { 1488522236LL };
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:75:32: warning: 'dc_fixpt_ln2' defined but not used [-Wunused-const-variable=]
75 | static const struct fixed31_32 dc_fixpt_ln2 = { 2977044471LL };
| ^~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:74:32: warning: 'dc_fixpt_e' defined but not used [-Wunused-const-variable=]
74 | static const struct fixed31_32 dc_fixpt_e = { 11674931555LL };
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:73:32: warning: 'dc_fixpt_two_pi' defined but not used [-Wunused-const-variable=]
73 | static const struct fixed31_32 dc_fixpt_two_pi = { 26986075409LL };
| ^~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:72:32: warning: 'dc_fixpt_pi' defined but not used [-Wunused-const-variable=]
72 | static const struct fixed31_32 dc_fixpt_pi = { 13493037705LL };
| ^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:67:32: warning: 'dc_fixpt_zero' defined but not used [-Wunused-const-variable=]
67 | static const struct fixed31_32 dc_fixpt_zero = { 0 };
| ^~~~~~~~~~~~~
vim +/direct_poll +1233 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1210
1211 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)
1212 {
1213 int i, j;
1214 struct amdgpu_ring *ring;
1215 uint64_t cache_addr;
1216 uint64_t rb_addr;
1217 uint64_t ctx_addr;
1218 uint32_t param, resp, expected;
1219 uint32_t offset, cache_size;
1220 uint32_t tmp, timeout;
1221 uint32_t id;
1222
1223 struct amdgpu_mm_table *table = &adev->virt.mm_table;
1224 uint32_t *table_loc;
1225 uint32_t table_size;
1226 uint32_t size, size_dw;
1227
1228 struct mmsch_v3_0_cmd_direct_write
1229 direct_wt = { {0} };
1230 struct mmsch_v3_0_cmd_direct_read_modify_write
1231 direct_rd_mod_wt = { {0} };
1232 struct mmsch_v3_0_cmd_direct_polling
> 1233 direct_poll = { {0} };
1234 struct mmsch_v3_0_cmd_end end = { {0} };
1235 struct mmsch_v3_0_init_header header;
1236
1237 direct_wt.cmd_header.command_type =
1238 MMSCH_COMMAND__DIRECT_REG_WRITE;
1239 direct_rd_mod_wt.cmd_header.command_type =
1240 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1241 direct_poll.cmd_header.command_type =
1242 MMSCH_COMMAND__DIRECT_REG_POLLING;
1243 end.cmd_header.command_type =
1244 MMSCH_COMMAND__END;
1245
1246 header.version = MMSCH_VERSION;
1247 header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2;
1248 for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) {
1249 header.inst[i].init_status = 0;
1250 header.inst[i].table_offset = 0;
1251 header.inst[i].table_size = 0;
1252 }
1253
1254 table_loc = (uint32_t *)table->cpu_addr;
1255 table_loc += header.total_size;
1256 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1257 if (adev->vcn.harvest_config & (1 << i))
1258 continue;
1259
1260 table_size = 0;
1261
1262 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i,
1263 mmUVD_STATUS),
1264 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
1265
1266 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
1267
1268 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1269 id = amdgpu_ucode_id_vcns[i];
1270 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1271 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1272 adev->firmware.ucode[id].tmr_mc_addr_lo);
1273 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1274 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1275 adev->firmware.ucode[id].tmr_mc_addr_hi);
1276 offset = 0;
1277 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1278 mmUVD_VCPU_CACHE_OFFSET0),
1279 0);
1280 } else {
1281 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1282 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1283 lower_32_bits(adev->vcn.inst[i].gpu_addr));
1284 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1285 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1286 upper_32_bits(adev->vcn.inst[i].gpu_addr));
1287 offset = cache_size;
1288 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1289 mmUVD_VCPU_CACHE_OFFSET0),
1290 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
1291 }
1292
1293 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1294 mmUVD_VCPU_CACHE_SIZE0),
1295 cache_size);
1296
1297 cache_addr = adev->vcn.inst[i].gpu_addr + offset;
1298 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1299 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1300 lower_32_bits(cache_addr));
1301 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1302 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1303 upper_32_bits(cache_addr));
1304 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1305 mmUVD_VCPU_CACHE_OFFSET1),
1306 0);
1307 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1308 mmUVD_VCPU_CACHE_SIZE1),
1309 AMDGPU_VCN_STACK_SIZE);
1310
1311 cache_addr = adev->vcn.inst[i].gpu_addr + offset +
1312 AMDGPU_VCN_STACK_SIZE;
1313 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1314 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1315 lower_32_bits(cache_addr));
1316 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1317 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1318 upper_32_bits(cache_addr));
1319 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1320 mmUVD_VCPU_CACHE_OFFSET2),
1321 0);
1322 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1323 mmUVD_VCPU_CACHE_SIZE2),
1324 AMDGPU_VCN_CONTEXT_SIZE);
1325
1326 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
1327 ring = &adev->vcn.inst[i].ring_enc[j];
1328 ring->wptr = 0;
1329 rb_addr = ring->gpu_addr;
1330 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1331 mmUVD_RB_BASE_LO),
1332 lower_32_bits(rb_addr));
1333 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1334 mmUVD_RB_BASE_HI),
1335 upper_32_bits(rb_addr));
1336 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1337 mmUVD_RB_SIZE),
1338 ring->ring_size / 4);
1339 }
1340
1341 ring = &adev->vcn.inst[i].ring_dec;
1342 ring->wptr = 0;
1343 rb_addr = ring->gpu_addr;
1344 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1345 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
1346 lower_32_bits(rb_addr));
1347 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1348 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
1349 upper_32_bits(rb_addr));
1350 /* force RBC into idle state */
1351 tmp = order_base_2(ring->ring_size);
1352 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);
1353 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1354 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1355 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1356 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1357 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1358 mmUVD_RBC_RB_CNTL),
1359 tmp);
1360
1361 /* add end packet */
1362 MMSCH_V3_0_INSERT_END();
1363
1364 /* refine header */
1365 header.inst[i].init_status = 1;
1366 header.inst[i].table_offset = header.total_size;
1367 header.inst[i].table_size = table_size;
1368 header.total_size += table_size;
1369 }
1370
1371 /* Update init table header in memory */
1372 size = sizeof(struct mmsch_v3_0_init_header);
1373 table_loc = (uint32_t *)table->cpu_addr;
1374 memcpy((void *)table_loc, &header, size);
1375
1376 /* message MMSCH (in VCN[0]) to initialize this client
1377 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
1378 * of memory descriptor location
1379 */
1380 ctx_addr = table->gpu_addr;
1381 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
1382 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));
1383
1384 /* 2, update vmid of descriptor */
1385 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID);
1386 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1387 /* use domain0 for MM scheduler */
1388 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1389 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp);
1390
1391 /* 3, notify mmsch about the size of this descriptor */
1392 size = header.total_size;
1393 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size);
1394
1395 /* 4, set resp to zero */
1396 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
1397
1398 /* 5, kick off the initialization and wait until
1399 * MMSCH_VF_MAILBOX_RESP becomes non-zero
1400 */
1401 param = 0x10000001;
1402 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param);
1403 tmp = 0;
1404 timeout = 1000;
1405 resp = 0;
1406 expected = param + 1;
1407 while (resp != expected) {
1408 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);
1409 if (resp == expected)
1410 break;
1411
1412 udelay(10);
1413 tmp = tmp + 10;
1414 if (tmp >= timeout) {
1415 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
1416 " waiting for mmMMSCH_VF_MAILBOX_RESP "\
1417 "(expected=0x%08x, readback=0x%08x)\n",
1418 tmp, expected, resp);
1419 return -EBUSY;
1420 }
1421 }
1422
1423 return 0;
1424 }
1425
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 25012 bytes --]
next reply other threads:[~2020-07-17 1:27 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-17 1:26 kernel test robot [this message]
2020-07-17 1:26 ` [radeon-alex:amd-staging-drm-next 1066/1110] drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c:1233:3: warning: variable 'direct_poll' set but not used kernel test robot
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=202007170954.9O7P4AwW%lkp@intel.com \
--to=lkp@intel.com \
--cc=Jack.Zhang1@amd.com \
--cc=dri-devel@lists.freedesktop.org \
--cc=kbuild-all@lists.01.org \
--cc=leo.liu@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.