From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Sasha Levin <sashal@kernel.org>,
"leilk.liu" <leilk.liu@mediatek.com>,
linux-spi@vger.kernel.org, Mark Brown <broonie@kernel.org>,
linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH AUTOSEL 5.7 13/40] spi: mediatek: use correct SPI_CFG2_REG MACRO
Date: Mon, 20 Jul 2020 17:36:48 -0400 [thread overview]
Message-ID: <20200720213715.406997-13-sashal@kernel.org> (raw)
In-Reply-To: <20200720213715.406997-1-sashal@kernel.org>
From: "leilk.liu" <leilk.liu@mediatek.com>
[ Upstream commit 44b37eb79e16a56cb30ba55b2da452396b941e7a ]
this patch use correct SPI_CFG2_REG offset.
Signed-off-by: leilk.liu <leilk.liu@mediatek.com>
Link: https://lore.kernel.org/r/20200701090020.7935-1-leilk.liu@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/spi/spi-mt65xx.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
index 6783e12c40c22..a556795caeef4 100644
--- a/drivers/spi/spi-mt65xx.c
+++ b/drivers/spi/spi-mt65xx.c
@@ -36,7 +36,6 @@
#define SPI_CFG0_SCK_LOW_OFFSET 8
#define SPI_CFG0_CS_HOLD_OFFSET 16
#define SPI_CFG0_CS_SETUP_OFFSET 24
-#define SPI_ADJUST_CFG0_SCK_LOW_OFFSET 16
#define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
#define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
@@ -48,6 +47,8 @@
#define SPI_CFG1_CS_IDLE_MASK 0xff
#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
+#define SPI_CFG2_SCK_HIGH_OFFSET 0
+#define SPI_CFG2_SCK_LOW_OFFSET 16
#define SPI_CMD_ACT BIT(0)
#define SPI_CMD_RESUME BIT(1)
@@ -283,7 +284,7 @@ static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
static void mtk_spi_prepare_transfer(struct spi_master *master,
struct spi_transfer *xfer)
{
- u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0;
+ u32 spi_clk_hz, div, sck_time, cs_time, reg_val;
struct mtk_spi *mdata = spi_master_get_devdata(master);
spi_clk_hz = clk_get_rate(mdata->spi_clk);
@@ -296,18 +297,18 @@ static void mtk_spi_prepare_transfer(struct spi_master *master,
cs_time = sck_time * 2;
if (mdata->dev_comp->enhance_timing) {
+ reg_val = (((sck_time - 1) & 0xffff)
+ << SPI_CFG2_SCK_HIGH_OFFSET);
reg_val |= (((sck_time - 1) & 0xffff)
- << SPI_CFG0_SCK_HIGH_OFFSET);
- reg_val |= (((sck_time - 1) & 0xffff)
- << SPI_ADJUST_CFG0_SCK_LOW_OFFSET);
+ << SPI_CFG2_SCK_LOW_OFFSET);
writel(reg_val, mdata->base + SPI_CFG2_REG);
- reg_val |= (((cs_time - 1) & 0xffff)
+ reg_val = (((cs_time - 1) & 0xffff)
<< SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
reg_val |= (((cs_time - 1) & 0xffff)
<< SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
writel(reg_val, mdata->base + SPI_CFG0_REG);
} else {
- reg_val |= (((sck_time - 1) & 0xff)
+ reg_val = (((sck_time - 1) & 0xff)
<< SPI_CFG0_SCK_HIGH_OFFSET);
reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
--
2.25.1
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: "leilk.liu" <leilk.liu@mediatek.com>,
Mark Brown <broonie@kernel.org>, Sasha Levin <sashal@kernel.org>,
linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Subject: [PATCH AUTOSEL 5.7 13/40] spi: mediatek: use correct SPI_CFG2_REG MACRO
Date: Mon, 20 Jul 2020 17:36:48 -0400 [thread overview]
Message-ID: <20200720213715.406997-13-sashal@kernel.org> (raw)
In-Reply-To: <20200720213715.406997-1-sashal@kernel.org>
From: "leilk.liu" <leilk.liu@mediatek.com>
[ Upstream commit 44b37eb79e16a56cb30ba55b2da452396b941e7a ]
this patch use correct SPI_CFG2_REG offset.
Signed-off-by: leilk.liu <leilk.liu@mediatek.com>
Link: https://lore.kernel.org/r/20200701090020.7935-1-leilk.liu@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/spi/spi-mt65xx.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
index 6783e12c40c22..a556795caeef4 100644
--- a/drivers/spi/spi-mt65xx.c
+++ b/drivers/spi/spi-mt65xx.c
@@ -36,7 +36,6 @@
#define SPI_CFG0_SCK_LOW_OFFSET 8
#define SPI_CFG0_CS_HOLD_OFFSET 16
#define SPI_CFG0_CS_SETUP_OFFSET 24
-#define SPI_ADJUST_CFG0_SCK_LOW_OFFSET 16
#define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
#define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
@@ -48,6 +47,8 @@
#define SPI_CFG1_CS_IDLE_MASK 0xff
#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
+#define SPI_CFG2_SCK_HIGH_OFFSET 0
+#define SPI_CFG2_SCK_LOW_OFFSET 16
#define SPI_CMD_ACT BIT(0)
#define SPI_CMD_RESUME BIT(1)
@@ -283,7 +284,7 @@ static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
static void mtk_spi_prepare_transfer(struct spi_master *master,
struct spi_transfer *xfer)
{
- u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0;
+ u32 spi_clk_hz, div, sck_time, cs_time, reg_val;
struct mtk_spi *mdata = spi_master_get_devdata(master);
spi_clk_hz = clk_get_rate(mdata->spi_clk);
@@ -296,18 +297,18 @@ static void mtk_spi_prepare_transfer(struct spi_master *master,
cs_time = sck_time * 2;
if (mdata->dev_comp->enhance_timing) {
+ reg_val = (((sck_time - 1) & 0xffff)
+ << SPI_CFG2_SCK_HIGH_OFFSET);
reg_val |= (((sck_time - 1) & 0xffff)
- << SPI_CFG0_SCK_HIGH_OFFSET);
- reg_val |= (((sck_time - 1) & 0xffff)
- << SPI_ADJUST_CFG0_SCK_LOW_OFFSET);
+ << SPI_CFG2_SCK_LOW_OFFSET);
writel(reg_val, mdata->base + SPI_CFG2_REG);
- reg_val |= (((cs_time - 1) & 0xffff)
+ reg_val = (((cs_time - 1) & 0xffff)
<< SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
reg_val |= (((cs_time - 1) & 0xffff)
<< SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
writel(reg_val, mdata->base + SPI_CFG0_REG);
} else {
- reg_val |= (((sck_time - 1) & 0xff)
+ reg_val = (((sck_time - 1) & 0xff)
<< SPI_CFG0_SCK_HIGH_OFFSET);
reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Sasha Levin <sashal@kernel.org>,
"leilk.liu" <leilk.liu@mediatek.com>,
linux-spi@vger.kernel.org, Mark Brown <broonie@kernel.org>,
linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH AUTOSEL 5.7 13/40] spi: mediatek: use correct SPI_CFG2_REG MACRO
Date: Mon, 20 Jul 2020 17:36:48 -0400 [thread overview]
Message-ID: <20200720213715.406997-13-sashal@kernel.org> (raw)
In-Reply-To: <20200720213715.406997-1-sashal@kernel.org>
From: "leilk.liu" <leilk.liu@mediatek.com>
[ Upstream commit 44b37eb79e16a56cb30ba55b2da452396b941e7a ]
this patch use correct SPI_CFG2_REG offset.
Signed-off-by: leilk.liu <leilk.liu@mediatek.com>
Link: https://lore.kernel.org/r/20200701090020.7935-1-leilk.liu@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/spi/spi-mt65xx.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
index 6783e12c40c22..a556795caeef4 100644
--- a/drivers/spi/spi-mt65xx.c
+++ b/drivers/spi/spi-mt65xx.c
@@ -36,7 +36,6 @@
#define SPI_CFG0_SCK_LOW_OFFSET 8
#define SPI_CFG0_CS_HOLD_OFFSET 16
#define SPI_CFG0_CS_SETUP_OFFSET 24
-#define SPI_ADJUST_CFG0_SCK_LOW_OFFSET 16
#define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
#define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
@@ -48,6 +47,8 @@
#define SPI_CFG1_CS_IDLE_MASK 0xff
#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
+#define SPI_CFG2_SCK_HIGH_OFFSET 0
+#define SPI_CFG2_SCK_LOW_OFFSET 16
#define SPI_CMD_ACT BIT(0)
#define SPI_CMD_RESUME BIT(1)
@@ -283,7 +284,7 @@ static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
static void mtk_spi_prepare_transfer(struct spi_master *master,
struct spi_transfer *xfer)
{
- u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0;
+ u32 spi_clk_hz, div, sck_time, cs_time, reg_val;
struct mtk_spi *mdata = spi_master_get_devdata(master);
spi_clk_hz = clk_get_rate(mdata->spi_clk);
@@ -296,18 +297,18 @@ static void mtk_spi_prepare_transfer(struct spi_master *master,
cs_time = sck_time * 2;
if (mdata->dev_comp->enhance_timing) {
+ reg_val = (((sck_time - 1) & 0xffff)
+ << SPI_CFG2_SCK_HIGH_OFFSET);
reg_val |= (((sck_time - 1) & 0xffff)
- << SPI_CFG0_SCK_HIGH_OFFSET);
- reg_val |= (((sck_time - 1) & 0xffff)
- << SPI_ADJUST_CFG0_SCK_LOW_OFFSET);
+ << SPI_CFG2_SCK_LOW_OFFSET);
writel(reg_val, mdata->base + SPI_CFG2_REG);
- reg_val |= (((cs_time - 1) & 0xffff)
+ reg_val = (((cs_time - 1) & 0xffff)
<< SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
reg_val |= (((cs_time - 1) & 0xffff)
<< SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
writel(reg_val, mdata->base + SPI_CFG0_REG);
} else {
- reg_val |= (((sck_time - 1) & 0xff)
+ reg_val = (((sck_time - 1) & 0xff)
<< SPI_CFG0_SCK_HIGH_OFFSET);
reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-07-20 21:37 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-20 21:36 [PATCH AUTOSEL 5.7 01/40] HID: i2c-hid: add Mediacom FlexBook edge13 to descriptor override Sasha Levin
2020-07-20 21:36 ` [PATCH AUTOSEL 5.7 02/40] HID: alps: support devices with report id 2 Sasha Levin
2020-07-20 21:36 ` [PATCH AUTOSEL 5.7 03/40] dmaengine: ti: k3-udma: Fix cleanup code for alloc_chan_resources Sasha Levin
2020-07-20 21:36 ` [PATCH AUTOSEL 5.7 04/40] dmaengine: ti: k3-udma: Fix the running channel handling in alloc_chan_resources Sasha Levin
2020-07-20 21:36 ` [PATCH AUTOSEL 5.7 05/40] HID: steam: fixes race in handling device list Sasha Levin
2020-07-20 21:36 ` [PATCH AUTOSEL 5.7 06/40] dmaengine: ti: k3-udma: add missing put_device() call in of_xudma_dev_get() Sasha Levin
2020-07-20 21:36 ` [PATCH AUTOSEL 5.7 07/40] dmaengine: idxd: fix hw descriptor fields for delta record Sasha Levin
2020-07-20 21:36 ` [PATCH AUTOSEL 5.7 08/40] HID: apple: Disable Fn-key key-re-mapping on clone keyboards Sasha Levin
2020-07-20 21:36 ` [PATCH AUTOSEL 5.7 09/40] dmaengine: tegra210-adma: Fix runtime PM imbalance on error Sasha Levin
2020-07-20 21:36 ` Sasha Levin
2020-07-20 21:36 ` [PATCH AUTOSEL 5.7 10/40] soc: amlogic: meson-gx-socinfo: Fix S905X3 and S905D3 ID's Sasha Levin
2020-07-20 21:36 ` Sasha Levin
2020-07-20 21:36 ` Sasha Levin
2020-07-20 21:36 ` [PATCH AUTOSEL 5.7 11/40] Input: add `SW_MACHINE_COVER` Sasha Levin
2020-07-20 21:36 ` [PATCH AUTOSEL 5.7 12/40] ARM: dts: n900: remove mmc1 card detect gpio Sasha Levin
2020-07-20 21:36 ` Sasha Levin [this message]
2020-07-20 21:36 ` [PATCH AUTOSEL 5.7 13/40] spi: mediatek: use correct SPI_CFG2_REG MACRO Sasha Levin
2020-07-20 21:36 ` Sasha Levin
2020-07-20 21:36 ` [PATCH AUTOSEL 5.7 14/40] regmap: dev_get_regmap_match(): fix string comparison Sasha Levin
2020-07-20 21:36 ` [PATCH AUTOSEL 5.7 15/40] hwmon: (aspeed-pwm-tacho) Avoid possible buffer overflow Sasha Levin
2020-07-20 21:36 ` Sasha Levin
2020-07-20 21:36 ` Sasha Levin
2020-07-20 21:36 ` [PATCH AUTOSEL 5.7 16/40] dmaengine: fsl-edma: fix wrong tcd endianness for big-endian cpu Sasha Levin
2020-07-20 21:36 ` [PATCH AUTOSEL 5.7 17/40] dmaengine: ioat setting ioat timeout as module parameter Sasha Levin
2020-07-20 21:36 ` [PATCH AUTOSEL 5.7 18/40] Input: synaptics - enable InterTouch for ThinkPad X1E 1st gen Sasha Levin
2020-07-20 21:36 ` [PATCH AUTOSEL 5.7 19/40] Input: elan_i2c - only increment wakeup count on touch Sasha Levin
2020-07-20 21:36 ` [PATCH AUTOSEL 5.7 20/40] usb: dwc3: pci: add support for the Intel Tiger Lake PCH -H variant Sasha Levin
2020-07-20 21:36 ` [PATCH AUTOSEL 5.7 21/40] usb: dwc3: pci: add support for the Intel Jasper Lake Sasha Levin
2020-07-20 21:36 ` [PATCH AUTOSEL 5.7 22/40] usb: gadget: udc: gr_udc: fix memleak on error handling path in gr_ep_init() Sasha Levin
2020-07-20 21:36 ` [PATCH AUTOSEL 5.7 23/40] usb: cdns3: ep0: fix some endian issues Sasha Levin
2020-07-20 21:36 ` [PATCH AUTOSEL 5.7 24/40] usb: cdns3: trace: " Sasha Levin
2020-07-20 21:37 ` [PATCH AUTOSEL 5.7 25/40] hwmon: (adm1275) Make sure we are reading enough data for different chips Sasha Levin
2020-07-20 21:37 ` [PATCH AUTOSEL 5.7 26/40] drm/amdgpu/gfx10: fix race condition for kiq Sasha Levin
2020-07-20 21:37 ` Sasha Levin
2020-07-20 21:37 ` Sasha Levin
2020-07-20 21:37 ` [PATCH AUTOSEL 5.7 27/40] drm/amdgpu: fix preemption unit test Sasha Levin
2020-07-20 21:37 ` Sasha Levin
2020-07-20 21:37 ` Sasha Levin
2020-07-20 21:37 ` [PATCH AUTOSEL 5.7 28/40] hwmon: (nct6775) Accept PECI Calibration as temperature source for NCT6798D Sasha Levin
2020-07-20 21:37 ` [PATCH AUTOSEL 5.7 29/40] platform/x86: ISST: Add new PCI device ids Sasha Levin
2020-07-20 21:37 ` [PATCH AUTOSEL 5.7 30/40] platform/x86: asus-wmi: allow BAT1 battery name Sasha Levin
2020-07-20 21:37 ` [PATCH AUTOSEL 5.7 31/40] hwmon: (scmi) Fix potential buffer overflow in scmi_hwmon_probe() Sasha Levin
2020-07-20 21:37 ` [PATCH AUTOSEL 5.7 32/40] ALSA: hda/realtek - fixup for yet another Intel reference board Sasha Levin
2020-07-20 21:37 ` Sasha Levin
2020-07-20 21:37 ` [PATCH AUTOSEL 5.7 33/40] drivers/perf: Fix kernel panic when rmmod PMU modules during perf sampling Sasha Levin
2020-07-20 21:37 ` Sasha Levin
2020-07-20 21:37 ` [PATCH AUTOSEL 5.7 34/40] arm64: Use test_tsk_thread_flag() for checking TIF_SINGLESTEP Sasha Levin
2020-07-20 21:37 ` Sasha Levin
2020-07-20 21:37 ` [PATCH AUTOSEL 5.7 35/40] x86: math-emu: Fix up 'cmp' insn for clang ias Sasha Levin
2020-07-20 21:37 ` [PATCH AUTOSEL 5.7 36/40] asm-generic/mmiowb: Allow mmiowb_set_pending() when preemptible() Sasha Levin
2020-07-20 21:37 ` Sasha Levin
2020-07-20 21:37 ` [PATCH AUTOSEL 5.7 37/40] drivers/perf: Prevent forced unbinding of PMU drivers Sasha Levin
2020-07-20 21:37 ` Sasha Levin
2020-07-20 21:37 ` [PATCH AUTOSEL 5.7 38/40] RISC-V: Upgrade smp_mb__after_spinlock() to iorw, iorw Sasha Levin
2020-07-20 21:37 ` [PATCH AUTOSEL 5.7 38/40] RISC-V: Upgrade smp_mb__after_spinlock() to iorw,iorw Sasha Levin
2020-07-20 21:37 ` [PATCH AUTOSEL 5.7 39/40] SUNRPC reverting d03727b248d0 ("NFSv4 fix CLOSE not waiting for direct IO compeletion") Sasha Levin
2020-07-20 21:37 ` [PATCH AUTOSEL 5.7 40/40] x86/boot: Don't add the EFI stub to targets Sasha Levin
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