From: Andrew Lunn <andrew@lunn.ch>
To: Russell King <rmk+kernel@armlinux.org.uk>
Cc: devicetree@vger.kernel.org, Jason Cooper <jason@lakedaemon.net>,
netdev@vger.kernel.org,
Gregory Clement <gregory.clement@bootlin.com>,
Kishon Vijay Abraham I <kishon@ti.com>,
Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>,
"David S. Miller" <davem@davemloft.net>,
linux-arm-kernel@lists.infradead.org,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Subject: Re: [PATCH v2 3/3] phy: armada-38x: fix NETA lockup when repeatedly switching speeds
Date: Tue, 21 Jul 2020 17:18:49 +0200 [thread overview]
Message-ID: <20200721151849.GR1339445@lunn.ch> (raw)
In-Reply-To: <E1jxtRj-0003Tz-CG@rmk-PC.armlinux.org.uk>
On Tue, Jul 21, 2020 at 03:40:43PM +0100, Russell King wrote:
> The mvneta hardware appears to lock up in various random ways when
> repeatedly switching speeds between 1G and 2.5G, which involves
> reprogramming the COMPHY. It is not entirely clear why this happens,
> but best guess is that reprogramming the COMPHY glitches mvneta clocks
> causing the hardware to fail. It seems that rebooting resolves the
> failure, but not down/up cycling the interface alone.
>
> Various other approaches have been tried, such as trying to cleanly
> power down the COMPHY and then take it back through the power up
> initialisation, but this does not seem to help.
>
> It was finally noticed that u-boot's last step when configuring a
> COMPHY for "SGMII" mode was to poke at a register described as
> "GBE_CONFIGURATION_REG", which is undocumented in any external
> documentation. All that we have is the fact that u-boot sets a bit
> corresponding to the "SGMII" lane at the end of COMPHY initialisation.
>
> Experimentation shows that if we clear this bit prior to changing the
> speed, and then set it afterwards, mvneta does not suffer this problem
> on the SolidRun Clearfog when switching speeds between 1G and 2.5G.
>
> This problem was found while script-testing phylink.
>
> This fix also requires the corresponding change to DT to be effective.
> See "ARM: dts: armada-38x: fix NETA lockup when repeatedly switching
> speeds".
>
> Fixes: 14dc100b4411 ("phy: armada38x: add common phy support")
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
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WARNING: multiple messages have this Message-ID (diff)
From: Andrew Lunn <andrew@lunn.ch>
To: Russell King <rmk+kernel@armlinux.org.uk>
Cc: Gregory Clement <gregory.clement@bootlin.com>,
Jason Cooper <jason@lakedaemon.net>,
Kishon Vijay Abraham I <kishon@ti.com>,
Rob Herring <robh+dt@kernel.org>,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
Vinod Koul <vkoul@kernel.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
"David S. Miller" <davem@davemloft.net>,
netdev@vger.kernel.org
Subject: Re: [PATCH v2 3/3] phy: armada-38x: fix NETA lockup when repeatedly switching speeds
Date: Tue, 21 Jul 2020 17:18:49 +0200 [thread overview]
Message-ID: <20200721151849.GR1339445@lunn.ch> (raw)
In-Reply-To: <E1jxtRj-0003Tz-CG@rmk-PC.armlinux.org.uk>
On Tue, Jul 21, 2020 at 03:40:43PM +0100, Russell King wrote:
> The mvneta hardware appears to lock up in various random ways when
> repeatedly switching speeds between 1G and 2.5G, which involves
> reprogramming the COMPHY. It is not entirely clear why this happens,
> but best guess is that reprogramming the COMPHY glitches mvneta clocks
> causing the hardware to fail. It seems that rebooting resolves the
> failure, but not down/up cycling the interface alone.
>
> Various other approaches have been tried, such as trying to cleanly
> power down the COMPHY and then take it back through the power up
> initialisation, but this does not seem to help.
>
> It was finally noticed that u-boot's last step when configuring a
> COMPHY for "SGMII" mode was to poke at a register described as
> "GBE_CONFIGURATION_REG", which is undocumented in any external
> documentation. All that we have is the fact that u-boot sets a bit
> corresponding to the "SGMII" lane at the end of COMPHY initialisation.
>
> Experimentation shows that if we clear this bit prior to changing the
> speed, and then set it afterwards, mvneta does not suffer this problem
> on the SolidRun Clearfog when switching speeds between 1G and 2.5G.
>
> This problem was found while script-testing phylink.
>
> This fix also requires the corresponding change to DT to be effective.
> See "ARM: dts: armada-38x: fix NETA lockup when repeatedly switching
> speeds".
>
> Fixes: 14dc100b4411 ("phy: armada38x: add common phy support")
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
next prev parent reply other threads:[~2020-07-21 15:20 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-21 14:37 [PATCH v2 0/3] Fix Armada 38x mvneta lockups when switching speeds Russell King - ARM Linux admin
2020-07-21 14:37 ` Russell King - ARM Linux admin
2020-07-21 14:40 ` [PATCH v2 1/3] dt: update Marvell Armada 38x COMPHY binding Russell King
2020-07-21 14:40 ` Russell King
2020-07-21 14:40 ` [PATCH v2 2/3] ARM: dts: armada-38x: fix NETA lockup when repeatedly switching speeds Russell King
2020-07-21 14:40 ` Russell King
2020-07-21 15:18 ` Andrew Lunn
2020-07-21 15:18 ` Andrew Lunn
2020-07-24 7:57 ` Gregory CLEMENT
2020-07-24 7:57 ` Gregory CLEMENT
2020-07-21 14:40 ` [PATCH v2 3/3] phy: " Russell King
2020-07-21 14:40 ` Russell King
2020-07-21 15:18 ` Andrew Lunn [this message]
2020-07-21 15:18 ` Andrew Lunn
2020-07-21 17:28 ` [PATCH v2 0/3] Fix Armada 38x mvneta lockups when " Vinod Koul
2020-07-21 17:28 ` Vinod Koul
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