* [PATCH 1/5] drm/amdgpu: add member to store vm fault interrupt masks
2020-07-21 10:29 [PATCH 0/5] drm/amdgpu: cleanup gmc v10 ip block Huang Rui
@ 2020-07-21 10:29 ` Huang Rui
2020-07-21 10:29 ` [PATCH 2/5] drm/amdgpu: abstract set_vm_fault_masks function to refine the programming Huang Rui
` (3 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Huang Rui @ 2020-07-21 10:29 UTC (permalink / raw)
To: amd-gfx; +Cc: Huang Rui
This patch adds a member in vmhub structure to store the vm fault interrupt
masks for different version gfxhubs/mmhubs.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 2 ++
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 8 ++++++++
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 8 ++++++++
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 8 ++++++++
4 files changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index acdb61c..e11c21a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -92,6 +92,8 @@ struct amdgpu_vmhub {
uint32_t ctx_addr_distance; /* include LO32/HI32 */
uint32_t eng_distance;
uint32_t eng_addr_distance; /* include LO32/HI32 */
+
+ uint32_t vm_cntx_cntl_vm_fault;
};
/*
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
index 394e6f5..993185f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
@@ -390,4 +390,12 @@ void gfxhub_v2_0_init(struct amdgpu_device *adev)
mmGCVM_INVALIDATE_ENG0_REQ;
hub->eng_addr_distance = mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
+
+ hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
index fa0bca3..07cae64 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
@@ -389,6 +389,14 @@ void gfxhub_v2_1_init(struct amdgpu_device *adev)
mmGCVM_INVALIDATE_ENG0_REQ;
hub->eng_addr_distance = mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
+
+ hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
}
int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index 757fa8e..48134b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -381,6 +381,14 @@ void mmhub_v2_0_init(struct amdgpu_device *adev)
mmMMVM_INVALIDATE_ENG0_REQ;
hub->eng_addr_distance = mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
+
+ hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
}
static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
--
2.7.4
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 2/5] drm/amdgpu: abstract set_vm_fault_masks function to refine the programming
2020-07-21 10:29 [PATCH 0/5] drm/amdgpu: cleanup gmc v10 ip block Huang Rui
2020-07-21 10:29 ` [PATCH 1/5] drm/amdgpu: add member to store vm fault interrupt masks Huang Rui
@ 2020-07-21 10:29 ` Huang Rui
2020-07-21 10:29 ` [PATCH 3/5] drm/amdgpu: add vmhub funcs helper Huang Rui
` (2 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Huang Rui @ 2020-07-21 10:29 UTC (permalink / raw)
To: amd-gfx; +Cc: Huang Rui
This patch is to add set_vm_fault_masks helper to amdgpu_gmc to refine the
original programming.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 20 +++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 4 +++
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 53 +++------------------------------
3 files changed, 28 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 34cbd6f..21d2c85 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -411,3 +411,23 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev)
break;
}
}
+
+void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,
+ bool enable)
+{
+ struct amdgpu_vmhub *hub;
+ u32 tmp, reg, i;
+
+ hub = &adev->vmhub[hub_type];
+ for (i = 0; i < 16; i++) {
+ reg = hub->vm_context0_cntl + hub->ctx_distance * i;
+
+ tmp = RREG32(reg);
+ if (enable)
+ tmp |= hub->vm_cntx_cntl_vm_fault;
+ else
+ tmp &= ~hub->vm_cntx_cntl_vm_fault;
+
+ WREG32(reg, tmp);
+ }
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index e11c21a..1785a0e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -291,4 +291,8 @@ int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev);
extern void amdgpu_gmc_tmz_set(struct amdgpu_device *adev);
+extern void
+amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,
+ bool enable);
+
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index ec90c62..e6c8526 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -62,63 +62,18 @@ gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *src, unsigned type,
enum amdgpu_interrupt_state state)
{
- struct amdgpu_vmhub *hub;
- u32 tmp, reg, bits[AMDGPU_MAX_VMHUBS], i;
-
- bits[AMDGPU_GFXHUB_0] = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
-
- bits[AMDGPU_MMHUB_0] = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
-
switch (state) {
case AMDGPU_IRQ_STATE_DISABLE:
/* MM HUB */
- hub = &adev->vmhub[AMDGPU_MMHUB_0];
- for (i = 0; i < 16; i++) {
- reg = hub->vm_context0_cntl + hub->ctx_distance * i;
- tmp = RREG32(reg);
- tmp &= ~bits[AMDGPU_MMHUB_0];
- WREG32(reg, tmp);
- }
-
+ amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false);
/* GFX HUB */
- hub = &adev->vmhub[AMDGPU_GFXHUB_0];
- for (i = 0; i < 16; i++) {
- reg = hub->vm_context0_cntl + hub->ctx_distance * i;
- tmp = RREG32(reg);
- tmp &= ~bits[AMDGPU_GFXHUB_0];
- WREG32(reg, tmp);
- }
+ amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false);
break;
case AMDGPU_IRQ_STATE_ENABLE:
/* MM HUB */
- hub = &adev->vmhub[AMDGPU_MMHUB_0];
- for (i = 0; i < 16; i++) {
- reg = hub->vm_context0_cntl + hub->ctx_distance * i;
- tmp = RREG32(reg);
- tmp |= bits[AMDGPU_MMHUB_0];
- WREG32(reg, tmp);
- }
-
+ amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true);
/* GFX HUB */
- hub = &adev->vmhub[AMDGPU_GFXHUB_0];
- for (i = 0; i < 16; i++) {
- reg = hub->vm_context0_cntl + hub->ctx_distance * i;
- tmp = RREG32(reg);
- tmp |= bits[AMDGPU_GFXHUB_0];
- WREG32(reg, tmp);
- }
+ amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true);
break;
default:
break;
--
2.7.4
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 3/5] drm/amdgpu: add vmhub funcs helper
2020-07-21 10:29 [PATCH 0/5] drm/amdgpu: cleanup gmc v10 ip block Huang Rui
2020-07-21 10:29 ` [PATCH 1/5] drm/amdgpu: add member to store vm fault interrupt masks Huang Rui
2020-07-21 10:29 ` [PATCH 2/5] drm/amdgpu: abstract set_vm_fault_masks function to refine the programming Huang Rui
@ 2020-07-21 10:29 ` Huang Rui
2020-07-22 8:15 ` Christian König
2020-07-21 10:29 ` [PATCH 4/5] drm/amdgpu: move get_invalidate_req function into gfxhub/mmhub level Huang Rui
2020-07-21 10:29 ` [PATCH 5/5] drm/amdgpu: won't include gc and mmhub register headers in GMC block Huang Rui
4 siblings, 1 reply; 9+ messages in thread
From: Huang Rui @ 2020-07-21 10:29 UTC (permalink / raw)
To: amd-gfx; +Cc: Huang Rui
This patch is to introduce vmhub funcs helper to add following callback
(print_l2_protection_fault_status). Each GC/MMHUB register specific programming
should be in gfxhub/mmhub level.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 7 +++++++
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 34 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 34 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 25 ++---------------------
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 34 ++++++++++++++++++++++++++++++++
5 files changed, 111 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 1785a0e..bbecd87 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -74,6 +74,11 @@ struct amdgpu_gmc_fault {
/*
* VMHUB structures, functions & helpers
*/
+struct amdgpu_vmhub_funcs {
+ void (*print_l2_protection_fault_status)(struct amdgpu_device *adev,
+ uint32_t status);
+};
+
struct amdgpu_vmhub {
uint32_t ctx0_ptb_addr_lo32;
uint32_t ctx0_ptb_addr_hi32;
@@ -94,6 +99,8 @@ struct amdgpu_vmhub {
uint32_t eng_addr_distance; /* include LO32/HI32 */
uint32_t vm_cntx_cntl_vm_fault;
+
+ const struct amdgpu_vmhub_funcs *vmhub_funcs;
};
/*
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
index 993185f..14268ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
@@ -31,6 +31,33 @@
#include "soc15_common.h"
+static void
+gfxhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
+ uint32_t status)
+{
+ dev_err(adev->dev,
+ "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
+ status);
+ dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n",
+ REG_GET_FIELD(status,
+ GCVM_L2_PROTECTION_FAULT_STATUS, CID));
+ dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
+ REG_GET_FIELD(status,
+ GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
+ dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
+ REG_GET_FIELD(status,
+ GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
+ dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
+ REG_GET_FIELD(status,
+ GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
+ dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
+ REG_GET_FIELD(status,
+ GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
+ dev_err(adev->dev, "\t RW: 0x%lx\n",
+ REG_GET_FIELD(status,
+ GCVM_L2_PROTECTION_FAULT_STATUS, RW));
+}
+
u64 gfxhub_v2_0_get_fb_location(struct amdgpu_device *adev)
{
u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);
@@ -360,6 +387,10 @@ void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev,
WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
}
+static const struct amdgpu_vmhub_funcs gfxhub_v2_0_vmhub_funcs = {
+ .print_l2_protection_fault_status = gfxhub_v2_0_print_l2_protection_fault_status,
+};
+
void gfxhub_v2_0_init(struct amdgpu_device *adev)
{
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
@@ -398,4 +429,7 @@ void gfxhub_v2_0_init(struct amdgpu_device *adev)
GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
+
+ if (hub->vmhub_funcs == NULL)
+ hub->vmhub_funcs = &gfxhub_v2_0_vmhub_funcs;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
index 07cae64..45fbce7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
@@ -31,6 +31,33 @@
#include "soc15_common.h"
+static void
+gfxhub_v2_1_print_l2_protection_fault_status(struct amdgpu_device *adev,
+ uint32_t status)
+{
+ dev_err(adev->dev,
+ "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
+ status);
+ dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n",
+ REG_GET_FIELD(status,
+ GCVM_L2_PROTECTION_FAULT_STATUS, CID));
+ dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
+ REG_GET_FIELD(status,
+ GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
+ dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
+ REG_GET_FIELD(status,
+ GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
+ dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
+ REG_GET_FIELD(status,
+ GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
+ dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
+ REG_GET_FIELD(status,
+ GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
+ dev_err(adev->dev, "\t RW: 0x%lx\n",
+ REG_GET_FIELD(status,
+ GCVM_L2_PROTECTION_FAULT_STATUS, RW));
+}
+
u64 gfxhub_v2_1_get_fb_location(struct amdgpu_device *adev)
{
u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);
@@ -359,6 +386,10 @@ void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev,
WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
}
+static const struct amdgpu_vmhub_funcs gfxhub_v2_1_vmhub_funcs = {
+ .print_l2_protection_fault_status = gfxhub_v2_1_print_l2_protection_fault_status,
+};
+
void gfxhub_v2_1_init(struct amdgpu_device *adev)
{
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
@@ -397,6 +428,9 @@ void gfxhub_v2_1_init(struct amdgpu_device *adev)
GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
+
+ if (hub->vmhub_funcs == NULL)
+ hub->vmhub_funcs = &gfxhub_v2_1_vmhub_funcs;
}
int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index e6c8526..8f35e13 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -121,29 +121,8 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
task_info.task_name, task_info.pid);
dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n",
addr, entry->client_id);
- if (!amdgpu_sriov_vf(adev)) {
- dev_err(adev->dev,
- "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
- status);
- dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n",
- REG_GET_FIELD(status,
- GCVM_L2_PROTECTION_FAULT_STATUS, CID));
- dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
- REG_GET_FIELD(status,
- GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
- dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
- REG_GET_FIELD(status,
- GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
- dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
- REG_GET_FIELD(status,
- GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
- dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
- REG_GET_FIELD(status,
- GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
- dev_err(adev->dev, "\t RW: 0x%lx\n",
- REG_GET_FIELD(status,
- GCVM_L2_PROTECTION_FAULT_STATUS, RW));
- }
+ if (!amdgpu_sriov_vf(adev))
+ hub->vmhub_funcs->print_l2_protection_fault_status(adev, status);
}
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index 48134b9..fb634c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -36,6 +36,33 @@
#define mmDAGB0_CNTL_MISC2_Sienna_Cichlid 0x0070
#define mmDAGB0_CNTL_MISC2_Sienna_Cichlid_BASE_IDX 0
+static void
+mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
+ uint32_t status)
+{
+ dev_err(adev->dev,
+ "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
+ status);
+ dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n",
+ REG_GET_FIELD(status,
+ MMVM_L2_PROTECTION_FAULT_STATUS, CID));
+ dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
+ REG_GET_FIELD(status,
+ MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
+ dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
+ REG_GET_FIELD(status,
+ MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
+ dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
+ REG_GET_FIELD(status,
+ MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
+ dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
+ REG_GET_FIELD(status,
+ MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
+ dev_err(adev->dev, "\t RW: 0x%lx\n",
+ REG_GET_FIELD(status,
+ MMVM_L2_PROTECTION_FAULT_STATUS, RW));
+}
+
void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
uint64_t page_table_base)
{
@@ -351,6 +378,10 @@ void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
}
+static const struct amdgpu_vmhub_funcs mmhub_v2_0_vmhub_funcs = {
+ .print_l2_protection_fault_status = mmhub_v2_0_print_l2_protection_fault_status,
+};
+
void mmhub_v2_0_init(struct amdgpu_device *adev)
{
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
@@ -389,6 +420,9 @@ void mmhub_v2_0_init(struct amdgpu_device *adev)
MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
+
+ if (hub->vmhub_funcs == NULL)
+ hub->vmhub_funcs = &mmhub_v2_0_vmhub_funcs;
}
static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
--
2.7.4
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^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 3/5] drm/amdgpu: add vmhub funcs helper
2020-07-21 10:29 ` [PATCH 3/5] drm/amdgpu: add vmhub funcs helper Huang Rui
@ 2020-07-22 8:15 ` Christian König
2020-07-22 8:37 ` Huang Rui
0 siblings, 1 reply; 9+ messages in thread
From: Christian König @ 2020-07-22 8:15 UTC (permalink / raw)
To: Huang Rui, amd-gfx
Am 21.07.20 um 12:29 schrieb Huang Rui:
> This patch is to introduce vmhub funcs helper to add following callback
> (print_l2_protection_fault_status). Each GC/MMHUB register specific programming
> should be in gfxhub/mmhub level.
>
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 7 +++++++
> drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 34 ++++++++++++++++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 34 ++++++++++++++++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 25 ++---------------------
> drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 34 ++++++++++++++++++++++++++++++++
> 5 files changed, 111 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> index 1785a0e..bbecd87 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> @@ -74,6 +74,11 @@ struct amdgpu_gmc_fault {
> /*
> * VMHUB structures, functions & helpers
> */
> +struct amdgpu_vmhub_funcs {
> + void (*print_l2_protection_fault_status)(struct amdgpu_device *adev,
> + uint32_t status);
> +};
> +
> struct amdgpu_vmhub {
> uint32_t ctx0_ptb_addr_lo32;
> uint32_t ctx0_ptb_addr_hi32;
> @@ -94,6 +99,8 @@ struct amdgpu_vmhub {
> uint32_t eng_addr_distance; /* include LO32/HI32 */
>
> uint32_t vm_cntx_cntl_vm_fault;
> +
> + const struct amdgpu_vmhub_funcs *vmhub_funcs;
> };
>
> /*
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
> index 993185f..14268ea 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
> @@ -31,6 +31,33 @@
>
> #include "soc15_common.h"
>
> +static void
> +gfxhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
> + uint32_t status)
> +{
> + dev_err(adev->dev,
> + "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
> + status);
> + dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n",
> + REG_GET_FIELD(status,
> + GCVM_L2_PROTECTION_FAULT_STATUS, CID));
> + dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
> + REG_GET_FIELD(status,
> + GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
> + dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
> + REG_GET_FIELD(status,
> + GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
> + dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
> + REG_GET_FIELD(status,
> + GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
> + dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
> + REG_GET_FIELD(status,
> + GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
> + dev_err(adev->dev, "\t RW: 0x%lx\n",
> + REG_GET_FIELD(status,
> + GCVM_L2_PROTECTION_FAULT_STATUS, RW));
> +}
> +
> u64 gfxhub_v2_0_get_fb_location(struct amdgpu_device *adev)
> {
> u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);
> @@ -360,6 +387,10 @@ void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev,
> WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
> }
>
> +static const struct amdgpu_vmhub_funcs gfxhub_v2_0_vmhub_funcs = {
> + .print_l2_protection_fault_status = gfxhub_v2_0_print_l2_protection_fault_status,
> +};
> +
> void gfxhub_v2_0_init(struct amdgpu_device *adev)
> {
> struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
> @@ -398,4 +429,7 @@ void gfxhub_v2_0_init(struct amdgpu_device *adev)
> GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
> +
> + if (hub->vmhub_funcs == NULL)
> + hub->vmhub_funcs = &gfxhub_v2_0_vmhub_funcs;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> index 07cae64..45fbce7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> @@ -31,6 +31,33 @@
>
> #include "soc15_common.h"
>
> +static void
> +gfxhub_v2_1_print_l2_protection_fault_status(struct amdgpu_device *adev,
> + uint32_t status)
> +{
> + dev_err(adev->dev,
> + "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
> + status);
> + dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n",
> + REG_GET_FIELD(status,
> + GCVM_L2_PROTECTION_FAULT_STATUS, CID));
> + dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
> + REG_GET_FIELD(status,
> + GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
> + dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
> + REG_GET_FIELD(status,
> + GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
> + dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
> + REG_GET_FIELD(status,
> + GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
> + dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
> + REG_GET_FIELD(status,
> + GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
> + dev_err(adev->dev, "\t RW: 0x%lx\n",
> + REG_GET_FIELD(status,
> + GCVM_L2_PROTECTION_FAULT_STATUS, RW));
> +}
> +
> u64 gfxhub_v2_1_get_fb_location(struct amdgpu_device *adev)
> {
> u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);
> @@ -359,6 +386,10 @@ void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev,
> WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
> }
>
> +static const struct amdgpu_vmhub_funcs gfxhub_v2_1_vmhub_funcs = {
> + .print_l2_protection_fault_status = gfxhub_v2_1_print_l2_protection_fault_status,
> +};
> +
> void gfxhub_v2_1_init(struct amdgpu_device *adev)
> {
> struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
> @@ -397,6 +428,9 @@ void gfxhub_v2_1_init(struct amdgpu_device *adev)
> GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
> +
> + if (hub->vmhub_funcs == NULL)
> + hub->vmhub_funcs = &gfxhub_v2_1_vmhub_funcs;
> }
>
> int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index e6c8526..8f35e13 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -121,29 +121,8 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
> task_info.task_name, task_info.pid);
> dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n",
> addr, entry->client_id);
> - if (!amdgpu_sriov_vf(adev)) {
> - dev_err(adev->dev,
> - "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
> - status);
> - dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n",
> - REG_GET_FIELD(status,
> - GCVM_L2_PROTECTION_FAULT_STATUS, CID));
> - dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
> - REG_GET_FIELD(status,
> - GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
> - dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
> - REG_GET_FIELD(status,
> - GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
> - dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
> - REG_GET_FIELD(status,
> - GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
> - dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
> - REG_GET_FIELD(status,
> - GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
> - dev_err(adev->dev, "\t RW: 0x%lx\n",
> - REG_GET_FIELD(status,
> - GCVM_L2_PROTECTION_FAULT_STATUS, RW));
> - }
> + if (!amdgpu_sriov_vf(adev))
> + hub->vmhub_funcs->print_l2_protection_fault_status(adev, status);
> }
>
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> index 48134b9..fb634c1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> @@ -36,6 +36,33 @@
> #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid 0x0070
> #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid_BASE_IDX 0
>
> +static void
> +mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
> + uint32_t status)
> +{
> + dev_err(adev->dev,
> + "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
> + status);
> + dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n",
> + REG_GET_FIELD(status,
> + MMVM_L2_PROTECTION_FAULT_STATUS, CID));
> + dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
> + REG_GET_FIELD(status,
> + MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
> + dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
> + REG_GET_FIELD(status,
> + MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
> + dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
> + REG_GET_FIELD(status,
> + MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
> + dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
> + REG_GET_FIELD(status,
> + MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
> + dev_err(adev->dev, "\t RW: 0x%lx\n",
> + REG_GET_FIELD(status,
> + MMVM_L2_PROTECTION_FAULT_STATUS, RW));
> +}
> +
> void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
> uint64_t page_table_base)
> {
> @@ -351,6 +378,10 @@ void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
> WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
> }
>
> +static const struct amdgpu_vmhub_funcs mmhub_v2_0_vmhub_funcs = {
> + .print_l2_protection_fault_status = mmhub_v2_0_print_l2_protection_fault_status,
> +};
> +
> void mmhub_v2_0_init(struct amdgpu_device *adev)
> {
> struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
> @@ -389,6 +420,9 @@ void mmhub_v2_0_init(struct amdgpu_device *adev)
> MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
> +
> + if (hub->vmhub_funcs == NULL)
> + hub->vmhub_funcs = &mmhub_v2_0_vmhub_funcs;
Please assign that unconditionally here.
Apart from that the series looks good to me as well.
Christian.
> }
>
> static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
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^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 3/5] drm/amdgpu: add vmhub funcs helper
2020-07-22 8:15 ` Christian König
@ 2020-07-22 8:37 ` Huang Rui
0 siblings, 0 replies; 9+ messages in thread
From: Huang Rui @ 2020-07-22 8:37 UTC (permalink / raw)
To: Koenig, Christian; +Cc: amd-gfx@lists.freedesktop.org
On Wed, Jul 22, 2020 at 04:15:52PM +0800, Christian König wrote:
> Am 21.07.20 um 12:29 schrieb Huang Rui:
> > This patch is to introduce vmhub funcs helper to add following callback
> > (print_l2_protection_fault_status). Each GC/MMHUB register specific programming
> > should be in gfxhub/mmhub level.
> >
> > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 7 +++++++
> > drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 34 ++++++++++++++++++++++++++++++++
> > drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 34 ++++++++++++++++++++++++++++++++
> > drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 25 ++---------------------
> > drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 34 ++++++++++++++++++++++++++++++++
> > 5 files changed, 111 insertions(+), 23 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> > index 1785a0e..bbecd87 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> > @@ -74,6 +74,11 @@ struct amdgpu_gmc_fault {
> > /*
> > * VMHUB structures, functions & helpers
> > */
> > +struct amdgpu_vmhub_funcs {
> > + void (*print_l2_protection_fault_status)(struct amdgpu_device *adev,
> > + uint32_t status);
> > +};
> > +
> > struct amdgpu_vmhub {
> > uint32_t ctx0_ptb_addr_lo32;
> > uint32_t ctx0_ptb_addr_hi32;
> > @@ -94,6 +99,8 @@ struct amdgpu_vmhub {
> > uint32_t eng_addr_distance; /* include LO32/HI32 */
> >
> > uint32_t vm_cntx_cntl_vm_fault;
> > +
> > + const struct amdgpu_vmhub_funcs *vmhub_funcs;
> > };
> >
> > /*
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
> > index 993185f..14268ea 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
> > @@ -31,6 +31,33 @@
> >
> > #include "soc15_common.h"
> >
> > +static void
> > +gfxhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
> > + uint32_t status)
> > +{
> > + dev_err(adev->dev,
> > + "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
> > + status);
> > + dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n",
> > + REG_GET_FIELD(status,
> > + GCVM_L2_PROTECTION_FAULT_STATUS, CID));
> > + dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
> > + REG_GET_FIELD(status,
> > + GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
> > + dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
> > + REG_GET_FIELD(status,
> > + GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
> > + dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
> > + REG_GET_FIELD(status,
> > + GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
> > + dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
> > + REG_GET_FIELD(status,
> > + GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
> > + dev_err(adev->dev, "\t RW: 0x%lx\n",
> > + REG_GET_FIELD(status,
> > + GCVM_L2_PROTECTION_FAULT_STATUS, RW));
> > +}
> > +
> > u64 gfxhub_v2_0_get_fb_location(struct amdgpu_device *adev)
> > {
> > u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);
> > @@ -360,6 +387,10 @@ void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev,
> > WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
> > }
> >
> > +static const struct amdgpu_vmhub_funcs gfxhub_v2_0_vmhub_funcs = {
> > + .print_l2_protection_fault_status = gfxhub_v2_0_print_l2_protection_fault_status,
> > +};
> > +
> > void gfxhub_v2_0_init(struct amdgpu_device *adev)
> > {
> > struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
> > @@ -398,4 +429,7 @@ void gfxhub_v2_0_init(struct amdgpu_device *adev)
> > GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> > GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> > GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
> > +
> > + if (hub->vmhub_funcs == NULL)
> > + hub->vmhub_funcs = &gfxhub_v2_0_vmhub_funcs;
> > }
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> > index 07cae64..45fbce7 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> > @@ -31,6 +31,33 @@
> >
> > #include "soc15_common.h"
> >
> > +static void
> > +gfxhub_v2_1_print_l2_protection_fault_status(struct amdgpu_device *adev,
> > + uint32_t status)
> > +{
> > + dev_err(adev->dev,
> > + "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
> > + status);
> > + dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n",
> > + REG_GET_FIELD(status,
> > + GCVM_L2_PROTECTION_FAULT_STATUS, CID));
> > + dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
> > + REG_GET_FIELD(status,
> > + GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
> > + dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
> > + REG_GET_FIELD(status,
> > + GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
> > + dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
> > + REG_GET_FIELD(status,
> > + GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
> > + dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
> > + REG_GET_FIELD(status,
> > + GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
> > + dev_err(adev->dev, "\t RW: 0x%lx\n",
> > + REG_GET_FIELD(status,
> > + GCVM_L2_PROTECTION_FAULT_STATUS, RW));
> > +}
> > +
> > u64 gfxhub_v2_1_get_fb_location(struct amdgpu_device *adev)
> > {
> > u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);
> > @@ -359,6 +386,10 @@ void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev,
> > WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
> > }
> >
> > +static const struct amdgpu_vmhub_funcs gfxhub_v2_1_vmhub_funcs = {
> > + .print_l2_protection_fault_status = gfxhub_v2_1_print_l2_protection_fault_status,
> > +};
> > +
> > void gfxhub_v2_1_init(struct amdgpu_device *adev)
> > {
> > struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
> > @@ -397,6 +428,9 @@ void gfxhub_v2_1_init(struct amdgpu_device *adev)
> > GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> > GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> > GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
> > +
> > + if (hub->vmhub_funcs == NULL)
> > + hub->vmhub_funcs = &gfxhub_v2_1_vmhub_funcs;
> > }
> >
> > int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> > index e6c8526..8f35e13 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> > @@ -121,29 +121,8 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
> > task_info.task_name, task_info.pid);
> > dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n",
> > addr, entry->client_id);
> > - if (!amdgpu_sriov_vf(adev)) {
> > - dev_err(adev->dev,
> > - "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
> > - status);
> > - dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n",
> > - REG_GET_FIELD(status,
> > - GCVM_L2_PROTECTION_FAULT_STATUS, CID));
> > - dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
> > - REG_GET_FIELD(status,
> > - GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
> > - dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
> > - REG_GET_FIELD(status,
> > - GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
> > - dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
> > - REG_GET_FIELD(status,
> > - GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
> > - dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
> > - REG_GET_FIELD(status,
> > - GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
> > - dev_err(adev->dev, "\t RW: 0x%lx\n",
> > - REG_GET_FIELD(status,
> > - GCVM_L2_PROTECTION_FAULT_STATUS, RW));
> > - }
> > + if (!amdgpu_sriov_vf(adev))
> > + hub->vmhub_funcs->print_l2_protection_fault_status(adev, status);
> > }
> >
> > return 0;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> > index 48134b9..fb634c1 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> > @@ -36,6 +36,33 @@
> > #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid 0x0070
> > #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid_BASE_IDX 0
> >
> > +static void
> > +mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
> > + uint32_t status)
> > +{
> > + dev_err(adev->dev,
> > + "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
> > + status);
> > + dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n",
> > + REG_GET_FIELD(status,
> > + MMVM_L2_PROTECTION_FAULT_STATUS, CID));
> > + dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
> > + REG_GET_FIELD(status,
> > + MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
> > + dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
> > + REG_GET_FIELD(status,
> > + MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
> > + dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
> > + REG_GET_FIELD(status,
> > + MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
> > + dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
> > + REG_GET_FIELD(status,
> > + MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
> > + dev_err(adev->dev, "\t RW: 0x%lx\n",
> > + REG_GET_FIELD(status,
> > + MMVM_L2_PROTECTION_FAULT_STATUS, RW));
> > +}
> > +
> > void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
> > uint64_t page_table_base)
> > {
> > @@ -351,6 +378,10 @@ void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
> > WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
> > }
> >
> > +static const struct amdgpu_vmhub_funcs mmhub_v2_0_vmhub_funcs = {
> > + .print_l2_protection_fault_status = mmhub_v2_0_print_l2_protection_fault_status,
> > +};
> > +
> > void mmhub_v2_0_init(struct amdgpu_device *adev)
> > {
> > struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
> > @@ -389,6 +420,9 @@ void mmhub_v2_0_init(struct amdgpu_device *adev)
> > MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> > MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> > MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
> > +
> > + if (hub->vmhub_funcs == NULL)
> > + hub->vmhub_funcs = &mmhub_v2_0_vmhub_funcs;
>
> Please assign that unconditionally here.
>
Updated, thanks.
Ray
> Apart from that the series looks good to me as well.
>
> Christian.
>
> > }
> >
> > static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
>
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 4/5] drm/amdgpu: move get_invalidate_req function into gfxhub/mmhub level
2020-07-21 10:29 [PATCH 0/5] drm/amdgpu: cleanup gmc v10 ip block Huang Rui
` (2 preceding siblings ...)
2020-07-21 10:29 ` [PATCH 3/5] drm/amdgpu: add vmhub funcs helper Huang Rui
@ 2020-07-21 10:29 ` Huang Rui
2020-07-21 10:29 ` [PATCH 5/5] drm/amdgpu: won't include gc and mmhub register headers in GMC block Huang Rui
4 siblings, 0 replies; 9+ messages in thread
From: Huang Rui @ 2020-07-21 10:29 UTC (permalink / raw)
To: amd-gfx; +Cc: Huang Rui
This patch is to move get_invalidate_req into gfxhub/mmhub level. It will avoid
mismatch of the different gfxhub/mmhub register offsets and fields in the same
gmc block.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 1 +
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 21 +++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 21 +++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 26 +++-----------------------
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 21 +++++++++++++++++++++
5 files changed, 67 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index bbecd87..9d58c56 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -77,6 +77,7 @@ struct amdgpu_gmc_fault {
struct amdgpu_vmhub_funcs {
void (*print_l2_protection_fault_status)(struct amdgpu_device *adev,
uint32_t status);
+ uint32_t (*get_invalidate_req)(unsigned int vmid, uint32_t flush_type);
};
struct amdgpu_vmhub {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
index 14268ea..5294f18 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
@@ -31,6 +31,26 @@
#include "soc15_common.h"
+static uint32_t gfxhub_v2_0_get_invalidate_req(unsigned int vmid,
+ uint32_t flush_type)
+{
+ u32 req = 0;
+
+ /* invalidate using legacy mode on vmid*/
+ req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
+ PER_VMID_INVALIDATE_REQ, 1 << vmid);
+ req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
+ req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
+ req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
+ req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
+ req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
+ req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
+ req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
+ CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
+
+ return req;
+}
+
static void
gfxhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
uint32_t status)
@@ -389,6 +409,7 @@ void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev,
static const struct amdgpu_vmhub_funcs gfxhub_v2_0_vmhub_funcs = {
.print_l2_protection_fault_status = gfxhub_v2_0_print_l2_protection_fault_status,
+ .get_invalidate_req = gfxhub_v2_0_get_invalidate_req,
};
void gfxhub_v2_0_init(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
index 45fbce7..e7850f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
@@ -31,6 +31,26 @@
#include "soc15_common.h"
+static uint32_t gfxhub_v2_1_get_invalidate_req(unsigned int vmid,
+ uint32_t flush_type)
+{
+ u32 req = 0;
+
+ /* invalidate using legacy mode on vmid*/
+ req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
+ PER_VMID_INVALIDATE_REQ, 1 << vmid);
+ req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
+ req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
+ req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
+ req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
+ req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
+ req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
+ req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
+ CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
+
+ return req;
+}
+
static void
gfxhub_v2_1_print_l2_protection_fault_status(struct amdgpu_device *adev,
uint32_t status)
@@ -388,6 +408,7 @@ void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev,
static const struct amdgpu_vmhub_funcs gfxhub_v2_1_vmhub_funcs = {
.print_l2_protection_fault_status = gfxhub_v2_1_print_l2_protection_fault_status,
+ .get_invalidate_req = gfxhub_v2_1_get_invalidate_req,
};
void gfxhub_v2_1_init(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 8f35e13..a1798ec2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -139,26 +139,6 @@ static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;
}
-static uint32_t gmc_v10_0_get_invalidate_req(unsigned int vmid,
- uint32_t flush_type)
-{
- u32 req = 0;
-
- /* invalidate using legacy mode on vmid*/
- req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
- PER_VMID_INVALIDATE_REQ, 1 << vmid);
- req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
- req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
- req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
- req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
- req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
- req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
- req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
- CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
-
- return req;
-}
-
/**
* gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore
*
@@ -199,7 +179,7 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
{
bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub);
struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
- u32 inv_req = gmc_v10_0_get_invalidate_req(vmid, flush_type);
+ u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
u32 tmp;
/* Use register 17 for GART */
const unsigned eng = 17;
@@ -294,7 +274,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
const unsigned eng = 17;
- u32 inv_req = gmc_v10_0_get_invalidate_req(vmid, flush_type);
+ u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
@@ -425,7 +405,7 @@ static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
{
bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
- uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0);
+ uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
unsigned eng = ring->vm_inv_eng;
/*
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index fb634c1..749719f 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -36,6 +36,26 @@
#define mmDAGB0_CNTL_MISC2_Sienna_Cichlid 0x0070
#define mmDAGB0_CNTL_MISC2_Sienna_Cichlid_BASE_IDX 0
+static uint32_t mmhub_v2_0_get_invalidate_req(unsigned int vmid,
+ uint32_t flush_type)
+{
+ u32 req = 0;
+
+ /* invalidate using legacy mode on vmid*/
+ req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
+ PER_VMID_INVALIDATE_REQ, 1 << vmid);
+ req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
+ req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
+ req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
+ req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
+ req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
+ req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
+ req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
+ CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
+
+ return req;
+}
+
static void
mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
uint32_t status)
@@ -380,6 +400,7 @@ void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
static const struct amdgpu_vmhub_funcs mmhub_v2_0_vmhub_funcs = {
.print_l2_protection_fault_status = mmhub_v2_0_print_l2_protection_fault_status,
+ .get_invalidate_req = mmhub_v2_0_get_invalidate_req,
};
void mmhub_v2_0_init(struct amdgpu_device *adev)
--
2.7.4
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^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 5/5] drm/amdgpu: won't include gc and mmhub register headers in GMC block
2020-07-21 10:29 [PATCH 0/5] drm/amdgpu: cleanup gmc v10 ip block Huang Rui
` (3 preceding siblings ...)
2020-07-21 10:29 ` [PATCH 4/5] drm/amdgpu: move get_invalidate_req function into gfxhub/mmhub level Huang Rui
@ 2020-07-21 10:29 ` Huang Rui
2020-07-22 1:13 ` Alex Deucher
4 siblings, 1 reply; 9+ messages in thread
From: Huang Rui @ 2020-07-21 10:29 UTC (permalink / raw)
To: amd-gfx; +Cc: Huang Rui
All gc/mmhub register access and operation should be in gfxhub/mmhub level.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index a1798ec2..19051ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -28,8 +28,6 @@
#include "hdp/hdp_5_0_0_offset.h"
#include "hdp/hdp_5_0_0_sh_mask.h"
-#include "gc/gc_10_1_0_sh_mask.h"
-#include "mmhub/mmhub_2_0_0_sh_mask.h"
#include "athub/athub_2_0_0_sh_mask.h"
#include "athub/athub_2_0_0_offset.h"
#include "dcn/dcn_2_0_0_offset.h"
--
2.7.4
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^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 5/5] drm/amdgpu: won't include gc and mmhub register headers in GMC block
2020-07-21 10:29 ` [PATCH 5/5] drm/amdgpu: won't include gc and mmhub register headers in GMC block Huang Rui
@ 2020-07-22 1:13 ` Alex Deucher
0 siblings, 0 replies; 9+ messages in thread
From: Alex Deucher @ 2020-07-22 1:13 UTC (permalink / raw)
To: Huang Rui; +Cc: amd-gfx list
Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
On Tue, Jul 21, 2020 at 6:29 AM Huang Rui <ray.huang@amd.com> wrote:
>
> All gc/mmhub register access and operation should be in gfxhub/mmhub level.
>
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index a1798ec2..19051ce 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -28,8 +28,6 @@
>
> #include "hdp/hdp_5_0_0_offset.h"
> #include "hdp/hdp_5_0_0_sh_mask.h"
> -#include "gc/gc_10_1_0_sh_mask.h"
> -#include "mmhub/mmhub_2_0_0_sh_mask.h"
> #include "athub/athub_2_0_0_sh_mask.h"
> #include "athub/athub_2_0_0_offset.h"
> #include "dcn/dcn_2_0_0_offset.h"
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply [flat|nested] 9+ messages in thread