From: Daniel Palmer <daniel@0x0f.com>
To: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org, jason@lakedaemon.net, arnd@arndb.de,
maz@kernel.org, Daniel Palmer <daniel@0x0f.com>,
linux-kernel@vger.kernel.org, robh+dt@kernel.org,
tglx@linutronix.de
Subject: [PATCH 0/3] irqchip: mstar: msc313 intc driver
Date: Wed, 5 Aug 2020 20:00:49 +0900 [thread overview]
Message-ID: <20200805110052.2655487-1-daniel@0x0f.com> (raw)
This driver adds support for the interrupt controllers
present between the various IP blocks and the ARM GIC
in MStar/SigmaStar Armv7 SoCs.
All of the chips so far have two instances of this
controller.
One instance controls what are called "IRQ" interrupts
by the vendor code I have seen.
The other instance controls what are called "FIQ" interrupts
by the vendor code. Presumably because they can be FIQ
interrupts. Right now the FIQ bypass is disabled in the
GIC so they operate just the same as the IRQ interrupts.
The register layouts are the same for both. The FIQ one
needs to have the status bit cleared on EOI so that difference
is handled by a compatible string difference.
I initially made this an RFC because this is my first
interrupt controller driver and I expect to have made a
bunch of mistakes. I've cleaned this up a bit since then
but I still expect it's not 100% correct. Especially
the offset to map the INTC interrupt to the GIC interrupt.
Daniel Palmer (3):
dt: bindings: interrupt-controller: Add binding description for
msc313-intc
irqchip: mstar: msc313-intc interrupt controller driver
ARM: mstar: Add interrupt controller to base dtsi
.../mstar,msc313-intc.yaml | 79 +++++++
MAINTAINERS | 2 +
arch/arm/boot/dts/mstar-v7.dtsi | 20 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-msc313-intc.c | 210 ++++++++++++++++++
5 files changed, 312 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mstar,msc313-intc.yaml
create mode 100644 drivers/irqchip/irq-msc313-intc.c
--
2.27.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Daniel Palmer <daniel@0x0f.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org,
robh+dt@kernel.org, arnd@arndb.de,
Daniel Palmer <daniel@0x0f.com>
Subject: [PATCH 0/3] irqchip: mstar: msc313 intc driver
Date: Wed, 5 Aug 2020 20:00:49 +0900 [thread overview]
Message-ID: <20200805110052.2655487-1-daniel@0x0f.com> (raw)
This driver adds support for the interrupt controllers
present between the various IP blocks and the ARM GIC
in MStar/SigmaStar Armv7 SoCs.
All of the chips so far have two instances of this
controller.
One instance controls what are called "IRQ" interrupts
by the vendor code I have seen.
The other instance controls what are called "FIQ" interrupts
by the vendor code. Presumably because they can be FIQ
interrupts. Right now the FIQ bypass is disabled in the
GIC so they operate just the same as the IRQ interrupts.
The register layouts are the same for both. The FIQ one
needs to have the status bit cleared on EOI so that difference
is handled by a compatible string difference.
I initially made this an RFC because this is my first
interrupt controller driver and I expect to have made a
bunch of mistakes. I've cleaned this up a bit since then
but I still expect it's not 100% correct. Especially
the offset to map the INTC interrupt to the GIC interrupt.
Daniel Palmer (3):
dt: bindings: interrupt-controller: Add binding description for
msc313-intc
irqchip: mstar: msc313-intc interrupt controller driver
ARM: mstar: Add interrupt controller to base dtsi
.../mstar,msc313-intc.yaml | 79 +++++++
MAINTAINERS | 2 +
arch/arm/boot/dts/mstar-v7.dtsi | 20 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-msc313-intc.c | 210 ++++++++++++++++++
5 files changed, 312 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mstar,msc313-intc.yaml
create mode 100644 drivers/irqchip/irq-msc313-intc.c
--
2.27.0
next reply other threads:[~2020-08-05 11:03 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-05 11:00 Daniel Palmer [this message]
2020-08-05 11:00 ` [PATCH 0/3] irqchip: mstar: msc313 intc driver Daniel Palmer
2020-08-05 11:00 ` [PATCH 1/3] dt: bindings: interrupt-controller: Add binding description for msc313-intc Daniel Palmer
2020-08-05 11:00 ` Daniel Palmer
2020-08-06 14:10 ` Rob Herring
2020-08-06 14:10 ` Rob Herring
2020-08-06 14:15 ` Rob Herring
2020-08-06 14:15 ` Rob Herring
2020-08-06 14:46 ` Daniel Palmer
2020-08-06 14:46 ` Daniel Palmer
2020-08-05 11:00 ` [PATCH 2/3] irqchip: mstar: msc313-intc interrupt controller driver Daniel Palmer
2020-08-05 11:00 ` Daniel Palmer
2020-08-05 16:26 ` Marc Zyngier
2020-08-05 16:26 ` Marc Zyngier
2020-08-06 10:03 ` Daniel Palmer
2020-08-06 10:03 ` Daniel Palmer
2020-08-06 12:36 ` Marc Zyngier
2020-08-06 12:36 ` Marc Zyngier
2020-08-05 11:00 ` [PATCH 3/3] ARM: mstar: Add interrupt controller to base dtsi Daniel Palmer
2020-08-05 11:00 ` Daniel Palmer
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200805110052.2655487-1-daniel@0x0f.com \
--to=daniel@0x0f.com \
--cc=arnd@arndb.de \
--cc=devicetree@vger.kernel.org \
--cc=jason@lakedaemon.net \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=maz@kernel.org \
--cc=robh+dt@kernel.org \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.