From: Christoph Hellwig <hch@infradead.org>
To: Will Deacon <will@kernel.org>
Cc: janghyuck.kim@samsung.com, catalin.marinas@arm.com,
linux-kernel@vger.kernel.org, hyesoo.yu@samsung.com,
iommu@lists.linux-foundation.org,
Cho KyongHo <pullip.cho@samsung.com>,
robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/2] dma-mapping: introduce relaxed version of dma sync
Date: Tue, 18 Aug 2020 09:37:20 +0100 [thread overview]
Message-ID: <20200818083720.GA9451@infradead.org> (raw)
In-Reply-To: <20200818082852.GA15145@willie-the-truck>
On Tue, Aug 18, 2020 at 09:28:53AM +0100, Will Deacon wrote:
> On Tue, Aug 18, 2020 at 04:43:10PM +0900, Cho KyongHo wrote:
> > Cache maintenance operations in the most of CPU architectures needs
> > memory barrier after the cache maintenance for the DMAs to view the
> > region of the memory correctly. The problem is that memory barrier is
> > very expensive and dma_[un]map_sg() and dma_sync_sg_for_{device|cpu}()
> > involves the memory barrier per every single cache sg entry. In some
> > CPU micro-architecture, a single memory barrier consumes more time than
> > cache clean on 4KiB. It becomes more serious if the number of CPU cores
> > are larger.
>
> Have you got higher-level performance data for this change? It's more likely
> that the DSB is what actually forces the prior cache maintenance to
> complete, so it's important to look at the bigger picture, not just the
> apparent relative cost of these instructions.
>
> Also, it's a miracle that non-coherent DMA even works, so I'm not sure
> that we should be complicating the implementation like this to try to
> make it "fast".
And without not just an important in-tree user but one that actually
matters and can show how this is correct the whole proposal is complete
nonstarter.
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@infradead.org>
To: Will Deacon <will@kernel.org>
Cc: janghyuck.kim@samsung.com, catalin.marinas@arm.com,
joro@8bytes.org, linux-kernel@vger.kernel.org,
hyesoo.yu@samsung.com, iommu@lists.linux-foundation.org,
Cho KyongHo <pullip.cho@samsung.com>,
robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org,
m.szyprowski@samsung.com
Subject: Re: [PATCH 1/2] dma-mapping: introduce relaxed version of dma sync
Date: Tue, 18 Aug 2020 09:37:20 +0100 [thread overview]
Message-ID: <20200818083720.GA9451@infradead.org> (raw)
In-Reply-To: <20200818082852.GA15145@willie-the-truck>
On Tue, Aug 18, 2020 at 09:28:53AM +0100, Will Deacon wrote:
> On Tue, Aug 18, 2020 at 04:43:10PM +0900, Cho KyongHo wrote:
> > Cache maintenance operations in the most of CPU architectures needs
> > memory barrier after the cache maintenance for the DMAs to view the
> > region of the memory correctly. The problem is that memory barrier is
> > very expensive and dma_[un]map_sg() and dma_sync_sg_for_{device|cpu}()
> > involves the memory barrier per every single cache sg entry. In some
> > CPU micro-architecture, a single memory barrier consumes more time than
> > cache clean on 4KiB. It becomes more serious if the number of CPU cores
> > are larger.
>
> Have you got higher-level performance data for this change? It's more likely
> that the DSB is what actually forces the prior cache maintenance to
> complete, so it's important to look at the bigger picture, not just the
> apparent relative cost of these instructions.
>
> Also, it's a miracle that non-coherent DMA even works, so I'm not sure
> that we should be complicating the implementation like this to try to
> make it "fast".
And without not just an important in-tree user but one that actually
matters and can show how this is correct the whole proposal is complete
nonstarter.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@infradead.org>
To: Will Deacon <will@kernel.org>
Cc: Cho KyongHo <pullip.cho@samsung.com>,
joro@8bytes.org, catalin.marinas@arm.com,
iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, m.szyprowski@samsung.com,
robin.murphy@arm.com, janghyuck.kim@samsung.com,
hyesoo.yu@samsung.com
Subject: Re: [PATCH 1/2] dma-mapping: introduce relaxed version of dma sync
Date: Tue, 18 Aug 2020 09:37:20 +0100 [thread overview]
Message-ID: <20200818083720.GA9451@infradead.org> (raw)
In-Reply-To: <20200818082852.GA15145@willie-the-truck>
On Tue, Aug 18, 2020 at 09:28:53AM +0100, Will Deacon wrote:
> On Tue, Aug 18, 2020 at 04:43:10PM +0900, Cho KyongHo wrote:
> > Cache maintenance operations in the most of CPU architectures needs
> > memory barrier after the cache maintenance for the DMAs to view the
> > region of the memory correctly. The problem is that memory barrier is
> > very expensive and dma_[un]map_sg() and dma_sync_sg_for_{device|cpu}()
> > involves the memory barrier per every single cache sg entry. In some
> > CPU micro-architecture, a single memory barrier consumes more time than
> > cache clean on 4KiB. It becomes more serious if the number of CPU cores
> > are larger.
>
> Have you got higher-level performance data for this change? It's more likely
> that the DSB is what actually forces the prior cache maintenance to
> complete, so it's important to look at the bigger picture, not just the
> apparent relative cost of these instructions.
>
> Also, it's a miracle that non-coherent DMA even works, so I'm not sure
> that we should be complicating the implementation like this to try to
> make it "fast".
And without not just an important in-tree user but one that actually
matters and can show how this is correct the whole proposal is complete
nonstarter.
next prev parent reply other threads:[~2020-08-18 8:37 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20200818075050epcas2p15c780650f5f6b4a54ce731c273d24c98@epcas2p1.samsung.com>
2020-08-18 7:43 ` [PATCH 1/2] dma-mapping: introduce relaxed version of dma sync Cho KyongHo
2020-08-18 7:43 ` Cho KyongHo
2020-08-18 7:43 ` Cho KyongHo
2020-08-18 7:43 ` [PATCH 2/2] arm64: dma-mapping: add relaxed DMA sync Cho KyongHo
2020-08-18 7:43 ` Cho KyongHo
2020-08-18 7:43 ` Cho KyongHo
2020-08-18 8:28 ` [PATCH 1/2] dma-mapping: introduce relaxed version of dma sync Will Deacon
2020-08-18 8:28 ` Will Deacon
2020-08-18 8:28 ` Will Deacon
2020-08-18 8:37 ` Christoph Hellwig [this message]
2020-08-18 8:37 ` Christoph Hellwig
2020-08-18 8:37 ` Christoph Hellwig
2020-08-18 9:46 ` Cho KyongHo
2020-08-18 9:46 ` Cho KyongHo
2020-08-18 9:46 ` Cho KyongHo
2020-08-18 9:37 ` Cho KyongHo
2020-08-18 9:37 ` Cho KyongHo
2020-08-18 9:37 ` Cho KyongHo
2020-08-18 10:07 ` Will Deacon
2020-08-18 10:07 ` Will Deacon
2020-08-18 10:07 ` Will Deacon
2020-08-18 16:10 ` Christoph Hellwig
2020-08-18 16:10 ` Christoph Hellwig
2020-08-18 16:10 ` Christoph Hellwig
2020-08-19 2:01 ` Cho KyongHo
2020-08-19 2:01 ` Cho KyongHo
2020-08-19 2:01 ` Cho KyongHo
2020-08-19 1:24 ` Cho KyongHo
2020-08-19 1:24 ` Cho KyongHo
2020-08-19 1:24 ` Cho KyongHo
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