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From: Roger Pau Monne <roger.pau@citrix.com>
To: <xen-devel@lists.xenproject.org>
Cc: Roger Pau Monne <roger.pau@citrix.com>,
	Jun Nakajima <jun.nakajima@intel.com>,
	Kevin Tian <kevin.tian@intel.com>,
	Jan Beulich <jbeulich@suse.com>,
	Andrew Cooper <andrew.cooper3@citrix.com>, Wei Liu <wl@xen.org>
Subject: [PATCH v2 0/8] x86: switch default MSR behavior
Date: Thu, 20 Aug 2020 17:08:27 +0200	[thread overview]
Message-ID: <20200820150835.27440-1-roger.pau@citrix.com> (raw)

Hello,

The current series attempts to change the current MSR default handling
behavior, which is to silently drop writes to writable MSRs, and allow
reading any MSR not explicitly handled.

After this series access to MSRs not explicitly handled will trigger a
#GP fault. I've tested this series with osstest and it doesn't introduce
any regression, at least on the boxes selected for testing:

http://logs.test-lab.xenproject.org/osstest/logs/152630/

Thanks, Roger.

Andrew Cooper (2):
  x86/hvm: Disallow access to unknown MSRs
  x86/msr: Drop compatibility #GP handling in guest_{rd,wr}msr()

Roger Pau Monne (6):
  x86/vmx: handle writes to MISC_ENABLE MSR
  x86/svm: silently drop writes to SYSCFG and related MSRs
  x86/msr: explicitly handle AMD DE_CFG
  x86/svm: drop writes to BU_CFG on revF chips
  x86/pv: allow reading FEATURE_CONTROL MSR
  x86/pv: disallow access to unknown MSRs

 xen/arch/x86/hvm/svm/svm.c     | 38 ++++++++++++++----
 xen/arch/x86/hvm/vmx/vmx.c     | 31 ++++++---------
 xen/arch/x86/msr.c             | 71 +++++++++++++---------------------
 xen/arch/x86/pv/emul-priv-op.c | 18 +++++----
 4 files changed, 79 insertions(+), 79 deletions(-)

-- 
2.28.0



             reply	other threads:[~2020-08-20 15:09 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-20 15:08 Roger Pau Monne [this message]
2020-08-20 15:08 ` [PATCH v2 1/8] x86/vmx: handle writes to MISC_ENABLE MSR Roger Pau Monne
2020-08-20 15:08 ` [PATCH v2 2/8] x86/svm: silently drop writes to SYSCFG and related MSRs Roger Pau Monne
2020-08-27 15:03   ` Jan Beulich
2020-08-31 14:37     ` Roger Pau Monné
2020-08-31 14:45       ` Roger Pau Monné
2020-08-31 15:21         ` Jan Beulich
2020-08-31 15:20       ` Jan Beulich
2020-08-20 15:08 ` [PATCH v2 3/8] x86/msr: explicitly handle AMD DE_CFG Roger Pau Monne
2020-08-20 17:08   ` Andrew Cooper
2020-08-21 11:52     ` Roger Pau Monné
2020-08-21 14:03       ` Andrew Cooper
2020-08-21 14:09         ` Roger Pau Monné
2020-08-20 15:08 ` [PATCH v2 4/8] x86/svm: drop writes to BU_CFG on revF chips Roger Pau Monne
2020-08-27 15:42   ` Jan Beulich
2020-08-20 15:08 ` [PATCH v2 5/8] x86/pv: allow reading FEATURE_CONTROL MSR Roger Pau Monne
2020-08-27 15:53   ` Jan Beulich
2020-08-31 15:12     ` Roger Pau Monné
2020-08-31 15:25       ` Jan Beulich
2020-08-20 15:08 ` [PATCH v2 6/8] x86/pv: disallow access to unknown MSRs Roger Pau Monne
2020-08-28  8:45   ` Jan Beulich
2020-08-20 15:08 ` [PATCH v2 7/8] x86/hvm: Disallow " Roger Pau Monne
2020-08-28  8:51   ` Jan Beulich
2020-08-20 15:08 ` [PATCH v2 8/8] x86/msr: Drop compatibility #GP handling in guest_{rd, wr}msr() Roger Pau Monne
2020-08-28  8:55   ` [PATCH v2 8/8] x86/msr: Drop compatibility #GP handling in guest_{rd,wr}msr() Jan Beulich
2020-08-31 15:22     ` Roger Pau Monné

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