From: Roger Pau Monne <roger.pau@citrix.com>
To: <xen-devel@lists.xenproject.org>
Cc: "Andrew Cooper" <andrew.cooper3@citrix.com>,
"Jan Beulich" <jbeulich@suse.com>, "Wei Liu" <wl@xen.org>,
"Roger Pau Monné" <roger.pau@citrix.com>,
"Jun Nakajima" <jun.nakajima@intel.com>,
"Kevin Tian" <kevin.tian@intel.com>
Subject: [PATCH v2 7/8] x86/hvm: Disallow access to unknown MSRs
Date: Thu, 20 Aug 2020 17:08:34 +0200 [thread overview]
Message-ID: <20200820150835.27440-8-roger.pau@citrix.com> (raw)
In-Reply-To: <20200820150835.27440-1-roger.pau@citrix.com>
From: Andrew Cooper <andrew.cooper3@citrix.com>
Change the catch-all behavior for MSR not explicitly handled. Instead
of allow full read-access to the MSR space and silently dropping
writes return an exception when the MSR is not explicitly handled.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
[remove rdmsr_safe from default case in svm_msr_read_intercept]
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
---
Changes since v1:
- Fold chunk to remove explicit write handling of VMX MSRs just to
#GP.
- Remove catch-all rdmsr_safe in svm_msr_read_intercept.
---
xen/arch/x86/hvm/svm/svm.c | 11 ++++-------
xen/arch/x86/hvm/vmx/vmx.c | 16 ++++------------
2 files changed, 8 insertions(+), 19 deletions(-)
diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index 7586b77268..1e4458c184 100644
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -1952,9 +1952,6 @@ static int svm_msr_read_intercept(unsigned int msr, uint64_t *msr_content)
break;
default:
- if ( rdmsr_safe(msr, *msr_content) == 0 )
- break;
-
if ( boot_cpu_data.x86 == 0xf && msr == MSR_F10_BU_CFG )
{
/* Win2k8 x64 reads this MSR on revF chips, where it
@@ -1967,6 +1964,7 @@ static int svm_msr_read_intercept(unsigned int msr, uint64_t *msr_content)
break;
}
+ gdprintk(XENLOG_WARNING, "RDMSR 0x%08x unimplemented\n", msr);
goto gpf;
}
@@ -2154,10 +2152,9 @@ static int svm_msr_write_intercept(unsigned int msr, uint64_t msr_content)
break;
default:
- /* Match up with the RDMSR side; ultimately this should go away. */
- if ( rdmsr_safe(msr, msr_content) == 0 )
- break;
-
+ gdprintk(XENLOG_WARNING,
+ "WRMSR 0x%08x val 0x%016"PRIx64" unimplemented\n",
+ msr, msr_content);
goto gpf;
}
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index f6657af923..9cc9d81c41 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -3015,9 +3015,7 @@ static int vmx_msr_read_intercept(unsigned int msr, uint64_t *msr_content)
break;
}
- if ( rdmsr_safe(msr, *msr_content) == 0 )
- break;
-
+ gdprintk(XENLOG_WARNING, "RDMSR 0x%08x unimplemented\n", msr);
goto gp_fault;
}
@@ -3290,11 +3288,6 @@ static int vmx_msr_write_intercept(unsigned int msr, uint64_t msr_content)
__vmwrite(GUEST_IA32_DEBUGCTL, msr_content);
break;
- case MSR_IA32_FEATURE_CONTROL:
- case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
- /* None of these MSRs are writeable. */
- goto gp_fault;
-
case MSR_IA32_MISC_ENABLE:
/* Silently drop writes that don't change the reported value. */
if ( vmx_msr_read_intercept(msr, &tmp) != X86EMUL_OKAY ||
@@ -3320,10 +3313,9 @@ static int vmx_msr_write_intercept(unsigned int msr, uint64_t msr_content)
is_last_branch_msr(msr) )
break;
- /* Match up with the RDMSR side; ultimately this should go away. */
- if ( rdmsr_safe(msr, msr_content) == 0 )
- break;
-
+ gdprintk(XENLOG_WARNING,
+ "WRMSR 0x%08x val 0x%016"PRIx64" unimplemented\n",
+ msr, msr_content);
goto gp_fault;
}
--
2.28.0
next prev parent reply other threads:[~2020-08-20 15:10 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-20 15:08 [PATCH v2 0/8] x86: switch default MSR behavior Roger Pau Monne
2020-08-20 15:08 ` [PATCH v2 1/8] x86/vmx: handle writes to MISC_ENABLE MSR Roger Pau Monne
2020-08-20 15:08 ` [PATCH v2 2/8] x86/svm: silently drop writes to SYSCFG and related MSRs Roger Pau Monne
2020-08-27 15:03 ` Jan Beulich
2020-08-31 14:37 ` Roger Pau Monné
2020-08-31 14:45 ` Roger Pau Monné
2020-08-31 15:21 ` Jan Beulich
2020-08-31 15:20 ` Jan Beulich
2020-08-20 15:08 ` [PATCH v2 3/8] x86/msr: explicitly handle AMD DE_CFG Roger Pau Monne
2020-08-20 17:08 ` Andrew Cooper
2020-08-21 11:52 ` Roger Pau Monné
2020-08-21 14:03 ` Andrew Cooper
2020-08-21 14:09 ` Roger Pau Monné
2020-08-20 15:08 ` [PATCH v2 4/8] x86/svm: drop writes to BU_CFG on revF chips Roger Pau Monne
2020-08-27 15:42 ` Jan Beulich
2020-08-20 15:08 ` [PATCH v2 5/8] x86/pv: allow reading FEATURE_CONTROL MSR Roger Pau Monne
2020-08-27 15:53 ` Jan Beulich
2020-08-31 15:12 ` Roger Pau Monné
2020-08-31 15:25 ` Jan Beulich
2020-08-20 15:08 ` [PATCH v2 6/8] x86/pv: disallow access to unknown MSRs Roger Pau Monne
2020-08-28 8:45 ` Jan Beulich
2020-08-20 15:08 ` Roger Pau Monne [this message]
2020-08-28 8:51 ` [PATCH v2 7/8] x86/hvm: Disallow " Jan Beulich
2020-08-20 15:08 ` [PATCH v2 8/8] x86/msr: Drop compatibility #GP handling in guest_{rd, wr}msr() Roger Pau Monne
2020-08-28 8:55 ` [PATCH v2 8/8] x86/msr: Drop compatibility #GP handling in guest_{rd,wr}msr() Jan Beulich
2020-08-31 15:22 ` Roger Pau Monné
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