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From: Rob Herring <robh@kernel.org>
To: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Cc: devicetree@vger.kernel.org, "Jason Cooper" <jason@lakedaemon.net>,
	"Marc Zyngier" <maz@kernel.org>,
	linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org,
	"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Andreas Färber" <afaerber@suse.de>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v5 1/3] dt-bindings: interrupt-controller: Add Actions SIRQ controller binding
Date: Tue, 25 Aug 2020 16:09:13 -0600	[thread overview]
Message-ID: <20200825220913.GA1423455@bogus> (raw)
In-Reply-To: <6bd99d4a7e50904b57bb3ad050725fbb418874b7.1597852360.git.cristian.ciocaltea@gmail.com>

On Wed, Aug 19, 2020 at 07:37:56PM +0300, Cristian Ciocaltea wrote:
> Actions Semi Owl SoCs SIRQ interrupt controller is found in S500, S700
> and S900 SoCs and provides support for handling up to 3 external
> interrupt lines.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> ---
> Changes in v5:
>  - Updated controller description statements both in the commit message
>    and the binding doc
> 
>  .../actions,owl-sirq.yaml                     | 68 +++++++++++++++++++
>  1 file changed, 68 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml b/Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml
> new file mode 100644
> index 000000000000..cf9b7a514e4e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml
> @@ -0,0 +1,68 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/actions,owl-sirq.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Actions Semi Owl SoCs SIRQ interrupt controller
> +
> +maintainers:
> +  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> +  - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> +
> +description: |
> +  This interrupt controller is found in the Actions Semi Owl SoCs (S500, S700
> +  and S900) and provides support for handling up to 3 external interrupt lines.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +        - enum:
> +          - actions,s500-sirq
> +          - actions,s700-sirq
> +          - actions,s900-sirq
> +        - const: actions,owl-sirq
> +      - const: actions,owl-sirq

This should be dropped. You should always have the SoC specific 
compatible.

> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupt-controller: true
> +
> +  '#interrupt-cells':
> +    const: 2
> +    description:
> +      The first cell is the input IRQ number, between 0 and 2, while the second
> +      cell is the trigger type as defined in interrupt.txt in this directory.
> +
> +  'actions,ext-interrupts':
> +    description: |
> +      Contains the GIC SPI IRQ numbers mapped to the external interrupt
> +      lines. They shall be specified sequentially from output 0 to 2.
> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> +    minItems: 3
> +    maxItems: 3

Can't you use 'interrupts' here?

> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupt-controller
> +  - '#interrupt-cells'
> +  - 'actions,ext-interrupts'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    sirq: interrupt-controller@b01b0200 {
> +      compatible = "actions,s500-sirq", "actions,owl-sirq";
> +      reg = <0xb01b0200 0x4>;
> +      interrupt-controller;
> +      #interrupt-cells = <2>;
> +      actions,ext-interrupts = <13>, /* SIRQ0 */
> +                               <14>, /* SIRQ1 */
> +                               <15>; /* SIRQ2 */
> +    };
> +
> +...
> -- 
> 2.28.0
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Cc: "Thomas Gleixner" <tglx@linutronix.de>,
	"Jason Cooper" <jason@lakedaemon.net>,
	"Marc Zyngier" <maz@kernel.org>,
	"Andreas Färber" <afaerber@suse.de>,
	"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-actions@lists.infradead.org
Subject: Re: [PATCH v5 1/3] dt-bindings: interrupt-controller: Add Actions SIRQ controller binding
Date: Tue, 25 Aug 2020 16:09:13 -0600	[thread overview]
Message-ID: <20200825220913.GA1423455@bogus> (raw)
In-Reply-To: <6bd99d4a7e50904b57bb3ad050725fbb418874b7.1597852360.git.cristian.ciocaltea@gmail.com>

On Wed, Aug 19, 2020 at 07:37:56PM +0300, Cristian Ciocaltea wrote:
> Actions Semi Owl SoCs SIRQ interrupt controller is found in S500, S700
> and S900 SoCs and provides support for handling up to 3 external
> interrupt lines.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> ---
> Changes in v5:
>  - Updated controller description statements both in the commit message
>    and the binding doc
> 
>  .../actions,owl-sirq.yaml                     | 68 +++++++++++++++++++
>  1 file changed, 68 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml b/Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml
> new file mode 100644
> index 000000000000..cf9b7a514e4e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml
> @@ -0,0 +1,68 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/actions,owl-sirq.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Actions Semi Owl SoCs SIRQ interrupt controller
> +
> +maintainers:
> +  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> +  - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> +
> +description: |
> +  This interrupt controller is found in the Actions Semi Owl SoCs (S500, S700
> +  and S900) and provides support for handling up to 3 external interrupt lines.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +        - enum:
> +          - actions,s500-sirq
> +          - actions,s700-sirq
> +          - actions,s900-sirq
> +        - const: actions,owl-sirq
> +      - const: actions,owl-sirq

This should be dropped. You should always have the SoC specific 
compatible.

> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupt-controller: true
> +
> +  '#interrupt-cells':
> +    const: 2
> +    description:
> +      The first cell is the input IRQ number, between 0 and 2, while the second
> +      cell is the trigger type as defined in interrupt.txt in this directory.
> +
> +  'actions,ext-interrupts':
> +    description: |
> +      Contains the GIC SPI IRQ numbers mapped to the external interrupt
> +      lines. They shall be specified sequentially from output 0 to 2.
> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> +    minItems: 3
> +    maxItems: 3

Can't you use 'interrupts' here?

> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupt-controller
> +  - '#interrupt-cells'
> +  - 'actions,ext-interrupts'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    sirq: interrupt-controller@b01b0200 {
> +      compatible = "actions,s500-sirq", "actions,owl-sirq";
> +      reg = <0xb01b0200 0x4>;
> +      interrupt-controller;
> +      #interrupt-cells = <2>;
> +      actions,ext-interrupts = <13>, /* SIRQ0 */
> +                               <14>, /* SIRQ1 */
> +                               <15>; /* SIRQ2 */
> +    };
> +
> +...
> -- 
> 2.28.0
> 

  reply	other threads:[~2020-08-25 22:10 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-19 16:37 [PATCH v5 0/3] Add Actions Semi Owl family sirq support Cristian Ciocaltea
2020-08-19 16:37 ` Cristian Ciocaltea
2020-08-19 16:37 ` [PATCH v5 1/3] dt-bindings: interrupt-controller: Add Actions SIRQ controller binding Cristian Ciocaltea
2020-08-19 16:37   ` Cristian Ciocaltea
2020-08-25 22:09   ` Rob Herring [this message]
2020-08-25 22:09     ` Rob Herring
2020-08-26 21:42     ` Cristian Ciocaltea
2020-08-26 21:42       ` Cristian Ciocaltea
2020-08-26 22:48       ` Rob Herring
2020-08-26 22:48         ` Rob Herring
2020-08-27 10:06         ` Cristian Ciocaltea
2020-08-27 10:06           ` Cristian Ciocaltea
2020-08-27 10:35           ` Marc Zyngier
2020-08-27 10:35             ` Marc Zyngier
2020-08-27 15:24             ` Cristian Ciocaltea
2020-08-27 15:24               ` Cristian Ciocaltea
2020-08-27 15:42               ` Marc Zyngier
2020-08-27 15:42                 ` Marc Zyngier
2020-08-27 18:54                 ` Cristian Ciocaltea
2020-08-27 18:54                   ` Cristian Ciocaltea
2020-08-19 16:37 ` [PATCH v5 2/3] irqchip: Add Actions Semi Owl SIRQ controller Cristian Ciocaltea
2020-08-19 16:37   ` Cristian Ciocaltea
2020-08-19 16:37 ` [PATCH v5 3/3] MAINTAINERS: Add entries for " Cristian Ciocaltea
2020-08-19 16:37   ` Cristian Ciocaltea
2020-08-22 13:17 ` [PATCH v5 0/3] Add Actions Semi Owl family sirq support Manivannan Sadhasivam
2020-08-22 13:17   ` Manivannan Sadhasivam
2020-08-22 23:05   ` Cristian Ciocaltea
2020-08-22 23:05     ` Cristian Ciocaltea
2020-08-25  2:09     ` Manivannan Sadhasivam
2020-08-25  2:09       ` Manivannan Sadhasivam
2020-08-25  9:44       ` Cristian Ciocaltea
2020-08-25  9:44         ` Cristian Ciocaltea

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