From: Anshuman Gupta <anshuman.gupta@intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
Hariom Pandey <hariom.pandey@intel.com>,
Srinivas K <srinivasx.k@intel.com>
Subject: Re: [Intel-gfx] [PATCH v3 2/3] drm/i915/display: Disable DRRS when needed in fastsets
Date: Wed, 26 Aug 2020 12:50:24 +0530 [thread overview]
Message-ID: <20200826072023.GI25390@intel.com> (raw)
In-Reply-To: <20200825171331.17971-2-jose.souza@intel.com>
On 2020-08-25 at 10:13:30 -0700, José Roberto de Souza wrote:
> Changes in the configuration could cause PSR to be compatible and
> enabled so driver must also be able to disable DRRS when doing
> fastsets.
>
> v2: Fixed name of DRRS compute function (Anshuman)
LGTM
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/209
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/173
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/209
> Cc: Srinivas K <srinivasx.k@intel.com>
> Cc: Hariom Pandey <hariom.pandey@intel.com>
> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 71 +++++++++++++++++++++---
> drivers/gpu/drm/i915/display/intel_dp.h | 2 +
> 3 files changed, 65 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index de5b216561d8..ff05a852417c 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4012,7 +4012,7 @@ static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
>
> intel_psr_update(intel_dp, crtc_state, conn_state);
> intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
> - intel_edp_drrs_enable(intel_dp, crtc_state);
> + intel_edp_drrs_update(intel_dp, crtc_state);
>
> intel_panel_update_backlight(state, encoder, crtc_state, conn_state);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index a08d03c61b02..c57ac83bf563 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -7736,6 +7736,15 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
> refresh_rate);
> }
>
> +static void
> +intel_edp_drrs_enable_locked(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + dev_priv->drrs.busy_frontbuffer_bits = 0;
> + dev_priv->drrs.dp = intel_dp;
> +}
> +
> /**
> * intel_edp_drrs_enable - init drrs struct if supported
> * @intel_dp: DP struct
> @@ -7754,19 +7763,34 @@ void intel_edp_drrs_enable(struct intel_dp *intel_dp,
> drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n");
>
> mutex_lock(&dev_priv->drrs.mutex);
> +
> if (dev_priv->drrs.dp) {
> - drm_dbg_kms(&dev_priv->drm, "DRRS already enabled\n");
> + drm_warn(&dev_priv->drm, "DRRS already enabled\n");
> goto unlock;
> }
>
> - dev_priv->drrs.busy_frontbuffer_bits = 0;
> -
> - dev_priv->drrs.dp = intel_dp;
> + intel_edp_drrs_enable_locked(intel_dp);
>
> unlock:
> mutex_unlock(&dev_priv->drrs.mutex);
> }
>
> +static void
> +intel_edp_drrs_disable_locked(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
> + int refresh;
> +
> + refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode);
> + intel_dp_set_drrs_state(dev_priv, crtc_state, refresh);
> + }
> +
> + dev_priv->drrs.dp = NULL;
> +}
> +
> /**
> * intel_edp_drrs_disable - Disable DRRS
> * @intel_dp: DP struct
> @@ -7787,16 +7811,45 @@ void intel_edp_drrs_disable(struct intel_dp *intel_dp,
> return;
> }
>
> - if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
> - intel_dp_set_drrs_state(dev_priv, old_crtc_state,
> - drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
> -
> - dev_priv->drrs.dp = NULL;
> + intel_edp_drrs_disable_locked(intel_dp, old_crtc_state);
> mutex_unlock(&dev_priv->drrs.mutex);
>
> cancel_delayed_work_sync(&dev_priv->drrs.work);
> }
>
> +/**
> + * intel_edp_drrs_update - Update DRRS state
> + * @intel_dp: Intel DP
> + * @crtc_state: new CRTC state
> + *
> + * This function will update DRRS states, disabling or enabling DRRS when
> + * executing fastsets. For full modeset, intel_edp_drrs_disable() and
> + * intel_edp_drrs_enable() should be called instead.
> + */
> +void
> +intel_edp_drrs_update(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
> + return;
> +
> + mutex_lock(&dev_priv->drrs.mutex);
> +
> + /* New state matches current one? */
> + if (crtc_state->has_drrs == !!dev_priv->drrs.dp)
> + goto unlock;
> +
> + if (crtc_state->has_drrs)
> + intel_edp_drrs_enable_locked(intel_dp);
> + else
> + intel_edp_drrs_disable_locked(intel_dp, crtc_state);
> +
> +unlock:
> + mutex_unlock(&dev_priv->drrs.mutex);
> +}
> +
> static void intel_edp_drrs_downclock_work(struct work_struct *work)
> {
> struct drm_i915_private *dev_priv =
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index b901ab850cbd..057b2c152cbd 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -81,6 +81,8 @@ void intel_edp_drrs_enable(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state);
> void intel_edp_drrs_disable(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state);
> +void intel_edp_drrs_update(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state);
> void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
> unsigned int frontbuffer_bits);
> void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
> --
> 2.28.0
>
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next prev parent reply other threads:[~2020-08-26 7:32 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-25 17:13 [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Compute has_drrs after compute has_psr José Roberto de Souza
2020-08-25 17:13 ` [Intel-gfx] [PATCH v3 2/3] drm/i915/display: Disable DRRS when needed in fastsets José Roberto de Souza
2020-08-26 7:20 ` Anshuman Gupta [this message]
2020-08-25 17:13 ` [Intel-gfx] [PATCH v3 3/3] drm/i915/display: Fix DRRS debugfs José Roberto de Souza
2020-08-26 7:14 ` Anshuman Gupta
2020-08-25 17:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/3] drm/i915/display: Compute has_drrs after compute has_psr Patchwork
2020-08-25 18:50 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-08-27 16:54 ` Souza, Jose
2020-08-26 7:26 ` [Intel-gfx] [PATCH v3 1/3] " Anshuman Gupta
2020-08-26 16:47 ` Souza, Jose
2020-08-27 12:09 ` Anshuman Gupta
2020-08-27 16:51 ` Souza, Jose
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