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From: Fenghua Yu <fenghua.yu@intel.com>
To: Fenghua Yu <fenghua.yu@intel.com>
Cc: Jean-Philippe Brucker <jean-philippe@linaro.org>,
	Tony Luck <tony.luck@intel.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Ashok Raj <ashok.raj@intel.com>,
	Ravi V Shankar <ravi.v.shankar@intel.com>,
	Peter Zijlstra <peterz@infradead.org>, x86 <x86@kernel.org>,
	linux-kernel <linux-kernel@vger.kernel.org>,
	Christoph Hellwig <hch@infradead.org>,
	Dave Hansen <dave.hansen@intel.com>,
	iommu@lists.linux-foundation.org, Ingo Molnar <mingo@redhat.com>,
	Borislav Petkov <bp@alien8.de>,
	Jacob Jun Pan <jacob.jun.pan@intel.com>,
	Andy Lutomirski <luto@kernel.org>, H Peter Anvin <hpa@zytor.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	David Woodhouse <dwmw2@infradead.org>
Subject: Re: [PATCH v7 9/9] x86/mmu: Allocate/free PASID
Date: Thu, 3 Sep 2020 22:34:53 +0000	[thread overview]
Message-ID: <20200903223453.GA410113@otcwcpicx6.sc.intel.com> (raw)
In-Reply-To: <1598540794-132666-10-git-send-email-fenghua.yu@intel.com>

Hi, Thomas, Andy, et al,

On Thu, Aug 27, 2020 at 08:06:34AM -0700, Fenghua Yu wrote:
> A PASID is allocated for an "mm" the first time any thread binds
> to an SVM capable device and is freed from the "mm" when the SVM is
> unbound by the last thread. It's possible for the "mm" to have different
> PASID values in different binding/unbinding SVM cycles.
> 
> The mm's PASID (non-zero for valid PASID or 0 for invalid PASID) is
> propagated to per-thread PASID MSR for all threads within the mm through
> through IPI, context switch, or inherit to ensure a running thread has
> the right PASID MSR matching the mm's PASID.
> 
> Suggested-by: Andy Lutomirski <luto@kernel.org>
> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
> Reviewed-by: Tony Luck <tony.luck@intel.com>
> ---
> v7:
> - Don't fix up PASID in #GP. Instead, update the PASID MSR by IPI and
>   context switch after PASID allocation and free. Inherit PASID from
>   parent. (Andy)
> 
> Before v7:
> - Allocate a PASID for the mm and free it until mm exit.

This is a friendly reminder. Any comment on this series?

This patch (9/9) is essentially the only changed patch that implements
updating PASID MSR for a thread by IPI and context switch per Andy's
comment.

Thank you very much in advance!

-Fenghua
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

WARNING: multiple messages have this Message-ID (diff)
From: Fenghua Yu <fenghua.yu@intel.com>
To: Fenghua Yu <fenghua.yu@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
	H Peter Anvin <hpa@zytor.com>, Andy Lutomirski <luto@kernel.org>,
	Jean-Philippe Brucker <jean-philippe@linaro.org>,
	Christoph Hellwig <hch@infradead.org>,
	Peter Zijlstra <peterz@infradead.org>,
	David Woodhouse <dwmw2@infradead.org>,
	Lu Baolu <baolu.lu@linux.intel.com>,
	Dave Hansen <dave.hansen@intel.com>,
	Tony Luck <tony.luck@intel.com>, Ashok Raj <ashok.raj@intel.com>,
	Jacob Jun Pan <jacob.jun.pan@intel.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Sohil Mehta <sohil.mehta@intel.com>,
	Ravi V Shankar <ravi.v.shankar@intel.com>,
	linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>,
	iommu@lists.linux-foundation.org
Subject: Re: [PATCH v7 9/9] x86/mmu: Allocate/free PASID
Date: Thu, 3 Sep 2020 22:34:53 +0000	[thread overview]
Message-ID: <20200903223453.GA410113@otcwcpicx6.sc.intel.com> (raw)
In-Reply-To: <1598540794-132666-10-git-send-email-fenghua.yu@intel.com>

Hi, Thomas, Andy, et al,

On Thu, Aug 27, 2020 at 08:06:34AM -0700, Fenghua Yu wrote:
> A PASID is allocated for an "mm" the first time any thread binds
> to an SVM capable device and is freed from the "mm" when the SVM is
> unbound by the last thread. It's possible for the "mm" to have different
> PASID values in different binding/unbinding SVM cycles.
> 
> The mm's PASID (non-zero for valid PASID or 0 for invalid PASID) is
> propagated to per-thread PASID MSR for all threads within the mm through
> through IPI, context switch, or inherit to ensure a running thread has
> the right PASID MSR matching the mm's PASID.
> 
> Suggested-by: Andy Lutomirski <luto@kernel.org>
> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
> Reviewed-by: Tony Luck <tony.luck@intel.com>
> ---
> v7:
> - Don't fix up PASID in #GP. Instead, update the PASID MSR by IPI and
>   context switch after PASID allocation and free. Inherit PASID from
>   parent. (Andy)
> 
> Before v7:
> - Allocate a PASID for the mm and free it until mm exit.

This is a friendly reminder. Any comment on this series?

This patch (9/9) is essentially the only changed patch that implements
updating PASID MSR for a thread by IPI and context switch per Andy's
comment.

Thank you very much in advance!

-Fenghua

  reply	other threads:[~2020-09-03 22:34 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-27 15:06 [PATCH v7 0/9] x86: tag application address space for devices Fenghua Yu
2020-08-27 15:06 ` Fenghua Yu
2020-08-27 15:06 ` [PATCH v7 1/9] iommu: Change type of pasid to u32 Fenghua Yu
2020-08-27 15:06   ` Fenghua Yu
2020-09-04 10:46   ` Borislav Petkov
2020-09-04 10:46     ` Borislav Petkov
2020-09-04 16:06     ` Fenghua Yu
2020-09-04 16:06       ` Fenghua Yu
2020-09-04 19:45       ` Borislav Petkov
2020-09-04 19:45         ` Borislav Petkov
2020-09-04 20:47         ` Fenghua Yu
2020-09-04 20:47           ` Fenghua Yu
2020-09-04 20:53           ` Borislav Petkov
2020-09-04 20:53             ` Borislav Petkov
2020-08-27 15:06 ` [PATCH v7 2/9] iommu/vt-d: Change flags type to unsigned int in binding mm Fenghua Yu
2020-08-27 15:06   ` Fenghua Yu
2020-08-27 15:06 ` [PATCH v7 3/9] docs: x86: Add documentation for SVA (Shared Virtual Addressing) Fenghua Yu
2020-08-27 15:06   ` Fenghua Yu
2020-09-05 15:14   ` Borislav Petkov
2020-09-05 15:14     ` Borislav Petkov
2020-09-05 17:54   ` Randy Dunlap
2020-09-05 17:54     ` Randy Dunlap
2020-09-15  2:02     ` Fenghua Yu
2020-09-15  2:02       ` Fenghua Yu
2020-08-27 15:06 ` [PATCH v7 4/9] x86/cpufeatures: Enumerate ENQCMD and ENQCMDS instructions Fenghua Yu
2020-08-27 15:06   ` Fenghua Yu
2020-08-27 15:06 ` [PATCH v7 5/9] x86/fpu/xstate: Add supervisor PASID state for ENQCMD feature Fenghua Yu
2020-08-27 15:06   ` Fenghua Yu
2020-08-27 15:06 ` [PATCH v7 6/9] x86/msr-index: Define IA32_PASID MSR Fenghua Yu
2020-08-27 15:06   ` Fenghua Yu
2020-08-27 15:06 ` [PATCH v7 7/9] mm: Define pasid in mm Fenghua Yu
2020-08-27 15:06   ` Fenghua Yu
2020-08-27 15:06 ` [PATCH v7 8/9] x86/cpufeatures: Mark ENQCMD as disabled when configured out Fenghua Yu
2020-08-27 15:06   ` Fenghua Yu
2020-09-07 10:29   ` Borislav Petkov
2020-09-07 10:29     ` Borislav Petkov
2020-08-27 15:06 ` [PATCH v7 9/9] x86/mmu: Allocate/free PASID Fenghua Yu
2020-08-27 15:06   ` Fenghua Yu
2020-09-03 22:34   ` Fenghua Yu [this message]
2020-09-03 22:34     ` Fenghua Yu
2020-09-07 11:18   ` Borislav Petkov
2020-09-07 11:18     ` Borislav Petkov
2020-09-14 18:37     ` Fenghua Yu
2020-09-14 18:37       ` Fenghua Yu
2020-09-14 19:25       ` Borislav Petkov
2020-09-14 19:25         ` Borislav Petkov

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