From: Stafford Horne <shorne@gmail.com>
To: openrisc@lists.librecores.org
Subject: [OpenRISC] [PATCH v2 2/3] openrisc: Fix cache API compile issue when not inlining
Date: Sat, 5 Sep 2020 22:19:34 +0900 [thread overview]
Message-ID: <20200905131935.972386-3-shorne@gmail.com> (raw)
In-Reply-To: <20200905131935.972386-1-shorne@gmail.com>
I found this when compiling a kbuild random config with GCC 11. The
config enables CONFIG_DEBUG_SECTION_MISMATCH, which sets CFLAGS
-fno-inline-functions-called-once. This causes the call to cache_loop in
cache.c to not be inlined causing the below compile error.
In file included from arch/openrisc/mm/cache.c:13:
arch/openrisc/mm/cache.c: In function 'cache_loop':
./arch/openrisc/include/asm/spr.h:16:27: warning: 'asm' operand 0 probably does not match constraints
16 | #define mtspr(_spr, _val) __asm__ __volatile__ ( \
| ^~~~~~~
arch/openrisc/mm/cache.c:25:3: note: in expansion of macro 'mtspr'
25 | mtspr(reg, line);
| ^~~~~
./arch/openrisc/include/asm/spr.h:16:27: error: impossible constraint in 'asm'
16 | #define mtspr(_spr, _val) __asm__ __volatile__ ( \
| ^~~~~~~
arch/openrisc/mm/cache.c:25:3: note: in expansion of macro 'mtspr'
25 | mtspr(reg, line);
| ^~~~~
make[1]: *** [scripts/Makefile.build:283: arch/openrisc/mm/cache.o] Error 1
The asm constraint "K" requires a immediate constant argument to mtspr,
however because of no inlining a register argument is passed causing a
failure. Fix this by using __always_inline.
Link: https://lore.kernel.org/lkml/202008200453.ohnhqkjQ%25lkp at intel.com/
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
arch/openrisc/mm/cache.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/openrisc/mm/cache.c b/arch/openrisc/mm/cache.c
index 08f56af387ac..534a52ec5e66 100644
--- a/arch/openrisc/mm/cache.c
+++ b/arch/openrisc/mm/cache.c
@@ -16,7 +16,7 @@
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
-static void cache_loop(struct page *page, const unsigned int reg)
+static __always_inline void cache_loop(struct page *page, const unsigned int reg)
{
unsigned long paddr = page_to_pfn(page) << PAGE_SHIFT;
unsigned long line = paddr & ~(L1_CACHE_BYTES - 1);
--
2.26.2
WARNING: multiple messages have this Message-ID (diff)
From: Stafford Horne <shorne@gmail.com>
To: LKML <linux-kernel@vger.kernel.org>
Cc: Stafford Horne <shorne@gmail.com>,
Jonas Bonn <jonas@southpole.se>,
Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>,
openrisc@lists.librecores.org
Subject: [PATCH v2 2/3] openrisc: Fix cache API compile issue when not inlining
Date: Sat, 5 Sep 2020 22:19:34 +0900 [thread overview]
Message-ID: <20200905131935.972386-3-shorne@gmail.com> (raw)
In-Reply-To: <20200905131935.972386-1-shorne@gmail.com>
I found this when compiling a kbuild random config with GCC 11. The
config enables CONFIG_DEBUG_SECTION_MISMATCH, which sets CFLAGS
-fno-inline-functions-called-once. This causes the call to cache_loop in
cache.c to not be inlined causing the below compile error.
In file included from arch/openrisc/mm/cache.c:13:
arch/openrisc/mm/cache.c: In function 'cache_loop':
./arch/openrisc/include/asm/spr.h:16:27: warning: 'asm' operand 0 probably does not match constraints
16 | #define mtspr(_spr, _val) __asm__ __volatile__ ( \
| ^~~~~~~
arch/openrisc/mm/cache.c:25:3: note: in expansion of macro 'mtspr'
25 | mtspr(reg, line);
| ^~~~~
./arch/openrisc/include/asm/spr.h:16:27: error: impossible constraint in 'asm'
16 | #define mtspr(_spr, _val) __asm__ __volatile__ ( \
| ^~~~~~~
arch/openrisc/mm/cache.c:25:3: note: in expansion of macro 'mtspr'
25 | mtspr(reg, line);
| ^~~~~
make[1]: *** [scripts/Makefile.build:283: arch/openrisc/mm/cache.o] Error 1
The asm constraint "K" requires a immediate constant argument to mtspr,
however because of no inlining a register argument is passed causing a
failure. Fix this by using __always_inline.
Link: https://lore.kernel.org/lkml/202008200453.ohnhqkjQ%25lkp@intel.com/
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
arch/openrisc/mm/cache.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/openrisc/mm/cache.c b/arch/openrisc/mm/cache.c
index 08f56af387ac..534a52ec5e66 100644
--- a/arch/openrisc/mm/cache.c
+++ b/arch/openrisc/mm/cache.c
@@ -16,7 +16,7 @@
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
-static void cache_loop(struct page *page, const unsigned int reg)
+static __always_inline void cache_loop(struct page *page, const unsigned int reg)
{
unsigned long paddr = page_to_pfn(page) << PAGE_SHIFT;
unsigned long line = paddr & ~(L1_CACHE_BYTES - 1);
--
2.26.2
next prev parent reply other threads:[~2020-09-05 13:19 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-05 13:19 [PATCH v2 0/3] OpenRISC fixes for 5.9 Stafford Horne
2020-09-05 13:19 ` [OpenRISC] [PATCH v2 1/3] openrisc: Reserve memblock for initrd Stafford Horne
2020-09-05 13:19 ` Stafford Horne
2020-09-05 13:25 ` [OpenRISC] " Stafford Horne
2020-09-05 13:25 ` Stafford Horne
2020-09-06 6:15 ` [OpenRISC] " Mike Rapoport
2020-09-06 6:15 ` Mike Rapoport
2020-09-05 13:19 ` Stafford Horne [this message]
2020-09-05 13:19 ` [PATCH v2 2/3] openrisc: Fix cache API compile issue when not inlining Stafford Horne
2020-09-05 13:19 ` [OpenRISC] [PATCH v2 3/3] openrisc: Fix issue with get_user for 64-bit values Stafford Horne
2020-09-05 13:19 ` Stafford Horne
2020-09-05 13:57 ` [OpenRISC] " Luc Van Oostenryck
2020-09-05 13:57 ` Luc Van Oostenryck
2020-09-05 21:34 ` [OpenRISC] " Stafford Horne
2020-09-05 21:34 ` Stafford Horne
2020-09-06 0:22 ` [OpenRISC] " Luc Van Oostenryck
2020-09-06 0:22 ` Luc Van Oostenryck
2020-09-06 21:00 ` Stafford Horne
2020-09-06 21:00 ` Stafford Horne
2020-09-05 13:24 ` [PATCH v2 0/3] OpenRISC fixes for 5.9 Stafford Horne
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