* [cip-dev] [PATCH 4.4.y-cip 0/4] Add RZ/G1H Audio support
@ 2020-09-11 12:31 Biju Das
2020-09-11 12:31 ` [cip-dev] [PATCH 4.4.y-cip 1/4] dt-bindings: ASoC: renesas,rsnd: Add r8a7742 support Biju Das
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: Biju Das @ 2020-09-11 12:31 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
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This patch series add audio support for iWave RZ/G1H board based on
r8a7742 SoC to 4.4.y-cip kernel. All patches in this series
are cherry-picked from mainline.
Lad Prabhakar (4):
dt-bindings: ASoC: renesas,rsnd: Add r8a7742 support
ARM: dts: r8a7742: Add audio support
ARM: dts: r8a7742-iwg21d-q7: Enable SGTL5000 audio codec
ARM: dts: r8a7742-iwg21d-q7: Sound DMA support via DVC on DTS
.../bindings/sound/renesas,rsnd.txt | 1 +
arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 100 +++++++
arch/arm/boot/dts/r8a7742.dtsi | 272 ++++++++++++++++++
3 files changed, 373 insertions(+)
--
2.17.1
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^ permalink raw reply [flat|nested] 8+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 1/4] dt-bindings: ASoC: renesas,rsnd: Add r8a7742 support 2020-09-11 12:31 [cip-dev] [PATCH 4.4.y-cip 0/4] Add RZ/G1H Audio support Biju Das @ 2020-09-11 12:31 ` Biju Das 2020-09-11 12:31 ` [cip-dev] [PATCH 4.4.y-cip 2/4] ARM: dts: r8a7742: Add audio support Biju Das ` (3 subsequent siblings) 4 siblings, 0 replies; 8+ messages in thread From: Biju Das @ 2020-09-11 12:31 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad [-- Attachment #1: Type: text/plain, Size: 1402 bytes --] From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> commit b6f10d3f2e6dfccf58c54e81c8af586b66a80ce4 upstream. Document RZ/G1H (R8A7742) SoC bindings. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1590526904-13855-2-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- Documentation/devicetree/bindings/sound/renesas,rsnd.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt index 23656d187f3a..bf07aa156a6a 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt @@ -6,6 +6,7 @@ Required properties: "renesas,rcar_sound-gen2" if generation2 (or RZ/G1) "renesas,rcar_sound-gen3" if generation3 Examples with soctypes are: + - "renesas,rcar_sound-r8a7742" (RZ/G1H) - "renesas,rcar_sound-r8a7743" (RZ/G1M) - "renesas,rcar_sound-r8a7744" (RZ/G1N) - "renesas,rcar_sound-r8a7745" (RZ/G1E) -- 2.17.1 [-- Attachment #2: Type: text/plain, Size: 419 bytes --] -=-=-=-=-=-=-=-=-=-=-=- Links: You receive all messages sent to this group. View/Reply Online (#5442): https://lists.cip-project.org/g/cip-dev/message/5442 Mute This Topic: https://lists.cip-project.org/mt/76778358/4520388 Group Owner: cip-dev+owner@lists.cip-project.org Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org] -=-=-=-=-=-=-=-=-=-=-=- ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [cip-dev] [PATCH 4.4.y-cip 2/4] ARM: dts: r8a7742: Add audio support 2020-09-11 12:31 [cip-dev] [PATCH 4.4.y-cip 0/4] Add RZ/G1H Audio support Biju Das 2020-09-11 12:31 ` [cip-dev] [PATCH 4.4.y-cip 1/4] dt-bindings: ASoC: renesas,rsnd: Add r8a7742 support Biju Das @ 2020-09-11 12:31 ` Biju Das 2020-09-11 12:32 ` [cip-dev] [PATCH 4.4.y-cip 3/4] ARM: dts: r8a7742-iwg21d-q7: Enable SGTL5000 audio codec Biju Das ` (2 subsequent siblings) 4 siblings, 0 replies; 8+ messages in thread From: Biju Das @ 2020-09-11 12:31 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad [-- Attachment #1: Type: text/plain, Size: 10546 bytes --] From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> commit 3816124fd0408ec98773409732035f8f8425ff50 upstream. Add sound support for the RZ/G1H SoC (a.k.a. R8A7742). This work is based on similar work done on the R8A7744 SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/1590526904-13855-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> [biju: changed clocks and power-domain properties, removed resets property] Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- arch/arm/boot/dts/r8a7742.dtsi | 272 +++++++++++++++++++++++++++++++++ 1 file changed, 272 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 32ed4138dc1b..e37f65655479 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -14,6 +14,27 @@ #address-cells = <2>; #size-cells = <2>; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + clocks { #address-cells = <2>; #size-cells = <2>; @@ -1180,6 +1201,257 @@ status = "disabled"; }; + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7742", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&mstp10_clks R8A7742_CLK_SSI_ALL>, + <&mstp10_clks R8A7742_CLK_SSI9>, <&mstp10_clks R8A7742_CLK_SSI8>, + <&mstp10_clks R8A7742_CLK_SSI7>, <&mstp10_clks R8A7742_CLK_SSI6>, + <&mstp10_clks R8A7742_CLK_SSI5>, <&mstp10_clks R8A7742_CLK_SSI4>, + <&mstp10_clks R8A7742_CLK_SSI3>, <&mstp10_clks R8A7742_CLK_SSI2>, + <&mstp10_clks R8A7742_CLK_SSI1>, <&mstp10_clks R8A7742_CLK_SSI0>, + <&mstp10_clks R8A7742_CLK_SCU_SRC9>, <&mstp10_clks R8A7742_CLK_SCU_SRC8>, + <&mstp10_clks R8A7742_CLK_SCU_SRC7>, <&mstp10_clks R8A7742_CLK_SCU_SRC6>, + <&mstp10_clks R8A7742_CLK_SCU_SRC5>, <&mstp10_clks R8A7742_CLK_SCU_SRC4>, + <&mstp10_clks R8A7742_CLK_SCU_SRC3>, <&mstp10_clks R8A7742_CLK_SCU_SRC2>, + <&mstp10_clks R8A7742_CLK_SCU_SRC1>, <&mstp10_clks R8A7742_CLK_SCU_SRC0>, + <&mstp10_clks R8A7742_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7742_CLK_SCU_CTU1_MIX1>, + <&mstp10_clks R8A7742_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7742_CLK_SCU_CTU1_MIX1>, + <&mstp10_clks R8A7742_CLK_SCU_DVC0>, <&mstp10_clks R8A7742_CLK_SCU_DVC1>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&m2_clk>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", + "src.5", "src.4", "src.3", "src.2", + "src.1", "src.0", + "ctu.0", "ctu.1", + "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&cpg_clocks>; + + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + rcar_sound,src { + src0: src-0 { + interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x01>, <&audma1 0x02>, + <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x03>, <&audma1 0x04>, + <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x05>, <&audma1 0x06>, + <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x07>, <&audma1 0x08>, + <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x09>, <&audma1 0x0a>, + <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0b>, <&audma1 0x0c>, + <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0d>, <&audma1 0x0e>, + <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0f>, <&audma1 0x10>, + <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x11>, <&audma1 0x12>, + <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x13>, <&audma1 0x14>, + <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + }; + }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7742", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&mstp5_clks R8A7742_CLK_AUDIO_DMAC0>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <13>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7742", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&mstp5_clks R8A7742_CLK_AUDIO_DMAC1>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <13>; + }; + sdhi0: mmc@ee100000 { compatible = "renesas,sdhi-r8a7742", "renesas,rcar-gen2-sdhi"; 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* [cip-dev] [PATCH 4.4.y-cip 3/4] ARM: dts: r8a7742-iwg21d-q7: Enable SGTL5000 audio codec 2020-09-11 12:31 [cip-dev] [PATCH 4.4.y-cip 0/4] Add RZ/G1H Audio support Biju Das 2020-09-11 12:31 ` [cip-dev] [PATCH 4.4.y-cip 1/4] dt-bindings: ASoC: renesas,rsnd: Add r8a7742 support Biju Das 2020-09-11 12:31 ` [cip-dev] [PATCH 4.4.y-cip 2/4] ARM: dts: r8a7742: Add audio support Biju Das @ 2020-09-11 12:32 ` Biju Das 2020-09-11 12:32 ` [cip-dev] [PATCH 4.4.y-cip 4/4] ARM: dts: r8a7742-iwg21d-q7: Sound DMA support via DVC on DTS Biju Das 2020-09-11 13:10 ` [cip-dev] [PATCH 4.4.y-cip 0/4] Add RZ/G1H Audio support Nobuhiro Iwamatsu 4 siblings, 0 replies; 8+ messages in thread From: Biju Das @ 2020-09-11 12:32 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad [-- Attachment #1: Type: text/plain, Size: 1962 bytes --] From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> commit 436765010f266a2afd6c9afd15233225448a3e8d upstream. This patch enables SGTL5000 audio codec on the carrier board. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1590611013-26029-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 37 +++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts index 1c7e58d47d73..8085e1651493 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts @@ -22,6 +22,20 @@ stdout-path = "serial2:115200n8"; }; + audio_clock: audio_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + reg_1p5v: 1p5v { + compatible = "regulator-fixed"; + regulator-name = "1P5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + vcc_sdhi2: regulator-vcc-sdhi2 { compatible = "regulator-fixed"; @@ -60,6 +74,24 @@ }; }; +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + reg = <0x0a>; + clocks = <&audio_clock>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + VDDD-supply = <®_1p5v>; + }; +}; + &cmt0 { status = "okay"; }; @@ -70,6 +102,11 @@ function = "avb"; }; + i2c2_pins: i2c2 { + groups = "i2c2_b"; + function = "i2c2"; + }; + scifa2_pins: scifa2 { groups = "scifa2_data_c"; function = "scifa2"; -- 2.17.1 [-- Attachment #2: Type: text/plain, Size: 419 bytes --] -=-=-=-=-=-=-=-=-=-=-=- Links: You receive all messages sent to this group. View/Reply Online (#5444): https://lists.cip-project.org/g/cip-dev/message/5444 Mute This Topic: https://lists.cip-project.org/mt/76778360/4520388 Group Owner: cip-dev+owner@lists.cip-project.org Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org] -=-=-=-=-=-=-=-=-=-=-=- ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [cip-dev] [PATCH 4.4.y-cip 4/4] ARM: dts: r8a7742-iwg21d-q7: Sound DMA support via DVC on DTS 2020-09-11 12:31 [cip-dev] [PATCH 4.4.y-cip 0/4] Add RZ/G1H Audio support Biju Das ` (2 preceding siblings ...) 2020-09-11 12:32 ` [cip-dev] [PATCH 4.4.y-cip 3/4] ARM: dts: r8a7742-iwg21d-q7: Enable SGTL5000 audio codec Biju Das @ 2020-09-11 12:32 ` Biju Das 2020-09-11 13:10 ` [cip-dev] [PATCH 4.4.y-cip 0/4] Add RZ/G1H Audio support Nobuhiro Iwamatsu 4 siblings, 0 replies; 8+ messages in thread From: Biju Das @ 2020-09-11 12:32 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad [-- Attachment #1: Type: text/plain, Size: 2813 bytes --] From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> commit fc3a1b2763d44ed471169e1dff2c8ce0fb352c1c upstream. Enable sound with DMA support on carrier board. DMA transfer uses DVC DMA DMApp [MEM] -> [SRC] -> [DVC] -> [SSIU] -> [SSI] DMA DMApp [MEM] <- [DVC] <- [SRC] <- [SSIU] <- [SSI] Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1590611013-26029-4-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 63 +++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts index 8085e1651493..428c494d88a3 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts @@ -5,6 +5,29 @@ * Copyright (C) 2020 Renesas Electronics Corp. */ +/* + * SSI-SGTL5000 + * + * This command is required when Playback/Capture + * + * amixer set "DVC Out" 100% + * amixer set "DVC In" 100% + * + * You can use Mute + * + * amixer set "DVC Out Mute" on + * amixer set "DVC In Mute" on + * + * You can use Volume Ramp + * + * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" + * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" + * amixer set "DVC Out Ramp" on + * aplay xxx.wav & + * amixer set "DVC Out" 80% // Volume Down + * amixer set "DVC Out" 100% // Volume Up + */ + /dts-v1/; #include "r8a7742-iwg21m.dtsi" @@ -36,6 +59,21 @@ regulator-always-on; }; + rsnd_sgtl5000: sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; + vcc_sdhi2: regulator-vcc-sdhi2 { compatible = "regulator-fixed"; @@ -117,6 +155,27 @@ function = "sdhi2"; power-source = <3300>; }; + + sound_pins: sound { + groups = "ssi34_ctrl", "ssi3_data", "ssi4_data"; + function = "ssi"; + }; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + rcar_sound,dai { + dai0 { + playback = <&ssi4 &src4 &dvc1>; + capture = <&ssi3 &src3 &dvc0>; + }; + }; }; &rwdt { @@ -141,3 +200,7 @@ wp-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; status = "okay"; }; + +&ssi4 { + shared-pin; +}; -- 2.17.1 [-- Attachment #2: Type: text/plain, Size: 419 bytes --] -=-=-=-=-=-=-=-=-=-=-=- Links: You receive all messages sent to this group. View/Reply Online (#5445): https://lists.cip-project.org/g/cip-dev/message/5445 Mute This Topic: https://lists.cip-project.org/mt/76778361/4520388 Group Owner: cip-dev+owner@lists.cip-project.org Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org] -=-=-=-=-=-=-=-=-=-=-=- ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [cip-dev] [PATCH 4.4.y-cip 0/4] Add RZ/G1H Audio support 2020-09-11 12:31 [cip-dev] [PATCH 4.4.y-cip 0/4] Add RZ/G1H Audio support Biju Das ` (3 preceding siblings ...) 2020-09-11 12:32 ` [cip-dev] [PATCH 4.4.y-cip 4/4] ARM: dts: r8a7742-iwg21d-q7: Sound DMA support via DVC on DTS Biju Das @ 2020-09-11 13:10 ` Nobuhiro Iwamatsu 2020-09-13 21:10 ` Pavel Machek 4 siblings, 1 reply; 8+ messages in thread From: Nobuhiro Iwamatsu @ 2020-09-11 13:10 UTC (permalink / raw) To: biju.das.jz, cip-dev, pavel; +Cc: chris.paterson2, prabhakar.mahadev-lad.rj [-- Attachment #1: Type: text/plain, Size: 1419 bytes --] Hi Biju, > -----Original Message----- > From: Biju Das [mailto:biju.das.jz@bp.renesas.com] > Sent: Friday, September 11, 2020 9:32 PM > To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ) > <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de> > Cc: Chris Paterson <chris.paterson2@renesas.com>; Biju Das <biju.das.jz@bp.renesas.com>; Prabhakar Mahadev Lad > <prabhakar.mahadev-lad.rj@bp.renesas.com> > Subject: [PATCH 4.4.y-cip 0/4] Add RZ/G1H Audio support > > This patch series add audio support for iWave RZ/G1H board based on > r8a7742 SoC to 4.4.y-cip kernel. All patches in this series > are cherry-picked from mainline. > > Lad Prabhakar (4): > dt-bindings: ASoC: renesas,rsnd: Add r8a7742 support > ARM: dts: r8a7742: Add audio support > ARM: dts: r8a7742-iwg21d-q7: Enable SGTL5000 audio codec > ARM: dts: r8a7742-iwg21d-q7: Sound DMA support via DVC on DTS > > .../bindings/sound/renesas,rsnd.txt | 1 + > arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 100 +++++++ > arch/arm/boot/dts/r8a7742.dtsi | 272 ++++++++++++++++++ > 3 files changed, 373 insertions(+) > I reviewd this patch series. Looks good to me. If If no objection, I will apply and push this. And I am testing on https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/188827239. Best regards, Nobuhiro [-- Attachment #2: Type: text/plain, Size: 419 bytes --] -=-=-=-=-=-=-=-=-=-=-=- Links: You receive all messages sent to this group. View/Reply Online (#5447): https://lists.cip-project.org/g/cip-dev/message/5447 Mute This Topic: https://lists.cip-project.org/mt/76778357/4520388 Group Owner: cip-dev+owner@lists.cip-project.org Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org] -=-=-=-=-=-=-=-=-=-=-=- ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [cip-dev] [PATCH 4.4.y-cip 0/4] Add RZ/G1H Audio support 2020-09-11 13:10 ` [cip-dev] [PATCH 4.4.y-cip 0/4] Add RZ/G1H Audio support Nobuhiro Iwamatsu @ 2020-09-13 21:10 ` Pavel Machek 2020-09-14 1:53 ` Nobuhiro Iwamatsu 0 siblings, 1 reply; 8+ messages in thread From: Pavel Machek @ 2020-09-13 21:10 UTC (permalink / raw) To: nobuhiro1.iwamatsu Cc: biju.das.jz, cip-dev, pavel, chris.paterson2, prabhakar.mahadev-lad.rj [-- Attachment #1.1: Type: text/plain, Size: 1139 bytes --] Hi! > > This patch series add audio support for iWave RZ/G1H board based on > > r8a7742 SoC to 4.4.y-cip kernel. All patches in this series > > are cherry-picked from mainline. > > > > Lad Prabhakar (4): > > dt-bindings: ASoC: renesas,rsnd: Add r8a7742 support > > ARM: dts: r8a7742: Add audio support > > ARM: dts: r8a7742-iwg21d-q7: Enable SGTL5000 audio codec > > ARM: dts: r8a7742-iwg21d-q7: Sound DMA support via DVC on DTS > > > > .../bindings/sound/renesas,rsnd.txt | 1 + > > arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 100 +++++++ > > arch/arm/boot/dts/r8a7742.dtsi | 272 ++++++++++++++++++ > > 3 files changed, 373 insertions(+) > > > > I reviewd this patch series. > Looks good to me. If If no objection, I will apply and push this. > And I am testing on https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/188827239. > Looks good to me, too. I have no objections. Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany [-- Attachment #1.2: Digital signature --] [-- Type: application/pgp-signature, Size: 181 bytes --] [-- Attachment #2: Type: text/plain, Size: 419 bytes --] -=-=-=-=-=-=-=-=-=-=-=- Links: You receive all messages sent to this group. View/Reply Online (#5448): https://lists.cip-project.org/g/cip-dev/message/5448 Mute This Topic: https://lists.cip-project.org/mt/76778357/4520388 Group Owner: cip-dev+owner@lists.cip-project.org Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org] -=-=-=-=-=-=-=-=-=-=-=- ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [cip-dev] [PATCH 4.4.y-cip 0/4] Add RZ/G1H Audio support 2020-09-13 21:10 ` Pavel Machek @ 2020-09-14 1:53 ` Nobuhiro Iwamatsu 0 siblings, 0 replies; 8+ messages in thread From: Nobuhiro Iwamatsu @ 2020-09-14 1:53 UTC (permalink / raw) To: pavel; +Cc: biju.das.jz, cip-dev, chris.paterson2, prabhakar.mahadev-lad.rj [-- Attachment #1: Type: text/plain, Size: 1512 bytes --] Hi, > -----Original Message----- > From: Pavel Machek [mailto:pavel@denx.de] > Sent: Monday, September 14, 2020 6:11 AM > To: iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ) <nobuhiro1.iwamatsu@toshiba.co.jp> > Cc: biju.das.jz@bp.renesas.com; cip-dev@lists.cip-project.org; pavel@denx.de; chris.paterson2@renesas.com; > prabhakar.mahadev-lad.rj@bp.renesas.com > Subject: Re: [PATCH 4.4.y-cip 0/4] Add RZ/G1H Audio support > > Hi! > > > > This patch series add audio support for iWave RZ/G1H board based on > > > r8a7742 SoC to 4.4.y-cip kernel. All patches in this series > > > are cherry-picked from mainline. > > > > > > Lad Prabhakar (4): > > > dt-bindings: ASoC: renesas,rsnd: Add r8a7742 support > > > ARM: dts: r8a7742: Add audio support > > > ARM: dts: r8a7742-iwg21d-q7: Enable SGTL5000 audio codec > > > ARM: dts: r8a7742-iwg21d-q7: Sound DMA support via DVC on DTS > > > > > > .../bindings/sound/renesas,rsnd.txt | 1 + > > > arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 100 +++++++ > > > arch/arm/boot/dts/r8a7742.dtsi | 272 ++++++++++++++++++ > > > 3 files changed, 373 insertions(+) > > > > > > > I reviewd this patch series. > > Looks good to me. If If no objection, I will apply and push this. > > And I am testing on https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/188827239. > > > > Looks good to me, too. I have no objections. Thanks! I applied and pushed. Best regards, Nobuhiro [-- Attachment #2: Type: text/plain, Size: 419 bytes --] -=-=-=-=-=-=-=-=-=-=-=- Links: You receive all messages sent to this group. View/Reply Online (#5449): https://lists.cip-project.org/g/cip-dev/message/5449 Mute This Topic: https://lists.cip-project.org/mt/76778357/4520388 Group Owner: cip-dev+owner@lists.cip-project.org Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org] -=-=-=-=-=-=-=-=-=-=-=- ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-09-14 1:54 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-09-11 12:31 [cip-dev] [PATCH 4.4.y-cip 0/4] Add RZ/G1H Audio support Biju Das 2020-09-11 12:31 ` [cip-dev] [PATCH 4.4.y-cip 1/4] dt-bindings: ASoC: renesas,rsnd: Add r8a7742 support Biju Das 2020-09-11 12:31 ` [cip-dev] [PATCH 4.4.y-cip 2/4] ARM: dts: r8a7742: Add audio support Biju Das 2020-09-11 12:32 ` [cip-dev] [PATCH 4.4.y-cip 3/4] ARM: dts: r8a7742-iwg21d-q7: Enable SGTL5000 audio codec Biju Das 2020-09-11 12:32 ` [cip-dev] [PATCH 4.4.y-cip 4/4] ARM: dts: r8a7742-iwg21d-q7: Sound DMA support via DVC on DTS Biju Das 2020-09-11 13:10 ` [cip-dev] [PATCH 4.4.y-cip 0/4] Add RZ/G1H Audio support Nobuhiro Iwamatsu 2020-09-13 21:10 ` Pavel Machek 2020-09-14 1:53 ` Nobuhiro Iwamatsu
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